SU1388897A1 - Device for performing matrix operations - Google Patents

Abstract

The invention relates to the field of computing technology and can be used in specialized computers and data processing devices. The purpose of the invention is to expand the functionality of the device due to the implementation of additional operations and the increase in speed. The goal is achieved by the fact that in a device containing tr of the same type of processor elements, where m and p are the dimensions of the matrices A and B, respectively, having three perHctpa, a multiplier and an adder, two registers are entered into each processor element,; three triggers, the element And and the element . AND-NO. A feature of the operation of the device is the parallel-flow organization of calculations, the synchronization of the execution of various parts of the algorithm. 3 il. with y (L

Description

from: 00 00

with

The invention relates to computing and can be used in specialized computers and data processing devices for performing C + AB operations on matrices.

The purpose of the invention is to expand the functional capabilities of the device by performing Additional Operations and increasing its speed.

Figure 1 shows a block diagram of a device for performing a matrix operation of C + AB with a matrix dimension: A- (3x2); B- (2x4); C- (3x4): for m 3, n 4ir 2; FIG. 2 - functional diagram of the connected 4 processor elements; in fig. 3 - timing charts of the device.

The device for performing the C + AB operations on the matrixes (Fig. 1) for, contains information inputs 1, 1,., And 1 3 of the first group, information inputs 2, 2, 2, 2, and 2e1 of the second group, information inputs 3, and 3 of the third group, input 4 sync pulses, processor elements 5, 5, i ,, and information outputs 6,, 6j, and 63 device groups ..

The processor element (figure 2) contains the first 7, second 8 and third 9 information inputs, register 10-14, triggers 15-17, multiplier 18, adder 19, element 20, element 21 and 21 as well as the first 22, second 23 and third 24 outs.

The operation of the device is based on the multiplication algorithm (txp) - the matrix A ajj. on (pchp) matrix b b; j which defines the resulting matrix D djj

dii cj. a;, b

Well - Kj I

1 i i m, 1 t j i n,

If d ° j C) j, TO at each subsequent recurrent step k 1, p many calculations are performed

 V

 a ;., b; k.

.J h - .k

The features of the operation of the device are the parallel organization of calculations, the synchronism of the execution of various parts of the algorithm, the shift of the accumulated sums:

from 0

5 o

..

five

about

five

d-- on the next tact of work from

five; -th processor element in 5, -2,4. | -and processor element (i l, m;, p-l) and writing elements a; to the appropriate ij-th processor element.

The device works as follows.

In the initial state, the registers 10-14 and the triggers 15-17 are set to the zero state. The elements (L-, 1) and (cjj, 1) are fed to the inputs on the e-clock cycle along with an additional bit. The sequence of submission of the elements of the matrices b and C are shown in the form of parallelograms in figure 1. Items in; served to the inputs of the processor elements without additional discharge; the order of feeding the elements of the matrix A is shown in the form of a triangle in FIG.

At the zero stroke, the elements a,, (b, 1) and (c °,, 1) are fed to the corresponding inputs of the elements 5,. On the leading edge of the clock pulse (figure 3). element a, is written to registers 11 and 12, since registers 11 and 12 are implemented on one-stroke triggers, and trigger 16 in the initial state allows writing to register 12. On the falling edge of the clock pulse, trigger 16 changes its state to the opposite and disables writing to the register 12. At the output of the NOT 2 element, a single signal is generated, which permits writing the element a ° to the register 13, which is also implemented on one-stroke triggers. Registers 10 and 14 are implemented on push-pull triggers, therefore, on the trailing edge of the clock pulse, elements with and are recorded respectively. Similarly, the push-pull triggers 15 and 17 are set to one unit by additional unit bits. From the output of the multiplier 18, the product a ,, b, is fed to the input of the adder 19, to the second input of which c is fed. At the output of the adder

d ,, c „+ a„ b ,,.

In the first cycle, the corresponding inputs of element 5c are supplied to elements a,

, (bji,) and (c, i)

to the corresponding inputs of the element 5, - (bj,, 1) and (d ,,, 1), to the corresponding inputs of the element 5, - a, (b,., I) and (c, 1).

In the element 5 "in the register 13 the element a is written.,, In the register 10 I,,

element with,, in register 14 - element

b11, d ,,, j is formed at the output of the adder. In the element 5,, i, the element a is written into the register 12, and the register 10 is d-d, and the register 14 is b |, j is formed at the output of the adder d, d, a, b, in the element 5, into the register 12 the element a is written to the register 10 - the element Cj, to the register 14 - b ,,, at the output of the adder d, c, + + a, b are formed.

In the second cycle in element 5, the element 12 is recorded in register 12 and the trigger 16 changes its state

and prohibits writing to register 12, on

, -i output of the adder is formed d,

 dii + 1. In elements 5 ;; in subsequent cycles, d, - are formed in a similar manner; shown in time diagrams (fig.Z).

The values of the corresponding elements d;: the resulting matrix D are formed at the corresponding outputs of the elements. The number of cycles

device equals (m + n + p-2). The duration of the device operation is determined by the expression

,

T tp t t.

Where. tp is the write time in register} tn multiplication time; tf. - summation time.

To perform the matrix operation C + AB over the new data stream, zero additional (K + 1) -e bits are fed to the inputs 1 and 3 of the elements 5- to set the triggers 16 in the initial state, which allow recording

elements a; j into registers 12.

To perform AB, AB, AB, etc. operations. in elements 5 ,. registers 12 contain the corresponding elements a

jj, inputs 1 are supplied, and

, T h - b

to inputs 3 - b ;.

Thus, the proposed device has more functionality than the known one, since in the latter only the multiplication of two patches is performed, and the proposed device implements matrix operations: matrix accumulation of C + AB; defined 5

d. . "G

-, "

and

25

thirty

35

45

50

55

chains of matrices AB, AB, AB, etc.

In addition, the proposed device has a structure with an arbitrary dimension of ha, n, and p.

Claims (1)

Invention Formula A device for performing matrix operations, where A is the size matrix (txp), B is the matrix (pxp), C is the matrix (gahp) containing txp of the same type of processor elements containing three registers, a multiplier, cyMMrftop, the information input of the i.1 st processor element (, m) is connected to the information input of the first group of the device, the second information inputs; d.1 th and lj-ro processor elements () are connected respectively to the il-M and 1.JM information inputs the second group of the device, the third information input lj-ro processor element This (, p) is connected to the jM informational input of the third group of the device, whose sync input is connected to the sync inputs ij-x of the processor elements, the first output of the iz-ro processor element (p-1) is connected to the first information input (i.zfl) -ro processor element, the second output i, j-ro of the processor element is connected to the second information input (, j + l) -ro of the processor element, the third output fj-ro of the processor element (, m-1) is connected to the third information input (f +1, j) -ro processor element, the first output of the ip-ro processor element Connected to the i-th output of the device group, characterized in that, in order to expand the functionality by performing additional operations and speeding up, two registers, three triggers, the AND element and the NOT element, and the first register information input are entered into each processing element and the information input of the first trigger is connected respectively to the bits from the first to the K-th and (K + 1) -th bit of the first information input of the processor element, where K is the matrix element size, the output of the first register the country is connected to the first input of the adder, the output of the adder and the output of the first trigger are connected respectively to the bits from the first to the K-th and (K + 1) -th bit of the first output of the processor element, the information input of the second register is connected to the second information input processor element, the enable input of the second register is connected to the input of the NOT element, the output of which is connected to the recording input of the fourth register, whose information input fo is combined with the information input of the third register and connected to you Odom second register, the fourth register output is connected to the second output of the processing element, the third write enable yhod PE t HCTpa connected to the output member and having a first input coupled to the data inputs of the first trig- fepa, and the second input - to informational the third trigger input, the information input of the fifth register and the information input of the third trigger are connected respectively to the bits from the first to the Kth and (K + 1) -th bit of the third information input of the processor element; the outputs of the third and fifth registers are connected respectively The first and second inputs of the multiplier, the output of which is connected to the second input of the adder, the output of the fifth register and the output of the third register are connected respectively to the bits from the first to the K-th and (K + 1) -th bit of the third output of the processor ele cient, write enable inputs of the first, second and fifth registers, the first, second and third flip-flops are combined and connected to the clock processing element.  at L 4 TJ | j-ra L - rf iL, 4JL, i / v it g gi2-y 4 "  / rSb " FI.2