SU1418736A1 - Device for analyzing graph parameters - Google Patents

Abstract

The invention relates to computing, can be used to study the shortest paths in the graph. The structure of the device introduced into groups of P shift registers, where B is the number of vertices in the graph, P is the number of edges in the graph. Before starting work, the information about the weight of the edges of the graph is entered into the shift registers of all groups, and the topology of the graph is determined by switching the corresponding contacts of the first and second type fields. After start-up, the device sequentially solves the problem of finding the shortest path using for this purpose service (senior) bits of the shift registers. This results in a reduction in hardware costs. 3 il.

Description

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 The invention relates to computing and can be used to explore paths in a graph.

The aim of the invention is to reduce hardware costs in determining the shortest path in the graph.

FIG. 1 shows a functional diagram of the device; in fig. 2 - timing diagram of the synchronization unit; in fig. 3 - topology of the graph, by the example of which the operation of the device will be considered. ; The device contains a block 1 of synchronization, the first matrix from B P ele fIeHTOB I 2, where B is the number of vertices of the graph, P is the number of edges in the graph, the second matrix from B P elements 3, the first group of B elements LI A, the first a group of B elements And 5, a group of B consecutive fumators 6, a second group of B elements of the And 7 elements, a second group of B elements of the OR 8, a third group of B elements of the 9 And 9, a third group of the B elements of the IL1-1 10, fourth group of B elements OR 11, first group of B triggers 12, second group of B triggers 13, group of B keys 14, group of B elements NOT 15, B groups of P registers 16 shift.

For greater clarity in FIG. 1, the first and second composable fields do not have numerical designations and are represented by the first group B of arrays of P Contacts 17 in each array of the first typed floor, the second group of B contacts 18 of the first typed floor, the first group of B arrays P on contacts 19 in each array of the second typesetting field and the second group of B arrays on P contacts 20 in each array of the second typesetting field.

In addition, in Fig. 1, digital indications have input 21 of the initial installation of the device, input 22 for starting the device, B inputs 23 setting the initial graph top, B inputs 23 setting the final graph tip, clock output 25 of synchronization unit 1, first synchronization output 26 of block 1 synchronization, the second synchronization output 27 of the synchronization unit 1 and the group of P synchronization outputs 28 of the synchronization unit 1.

The device works as follows.

Let it be necessary to find the shortest path from the first to the second vertex of the graph, whose topology is represented by

in fig. 3 (numbers without brackets indicate the numbers of vertices, numbers in parentheses — numbers of edges, numbers in square brackets — weight of the corresponding edges of the graph).

Before starting, the contacts of the first and second typed fields are connected according to the topology of the graph (the first typing field is used to solve the task of determining the shortest path, in the graph, the second typing field is used to indicate the vertices of the shortest path). For a graph whose topology is shown in FIG. 1, the first contact 18 of the second group of the first type-setting field is connected to the third contact 17 of the third array and to the second contact 17 of the fourth array of the first group of the first type-setting field,

the third contact 18 of the second group of the first type-setting field is connected to the first contact 17 of the second array of the first group of the first type-setting field, the fourth contact 18 of the second group

The first typesetting field is connected to the fourth contact of the second array of the first group of the first typesetting field. The first contact 20 of the second array of the second group of the second dial

the floor is connected to the first pin 19 of the third array of the first group of the second typesetting field, the fourth contact 20 of the second array of the second group of the second typesetting field is connected to the fourth contact 19 of the fourth array of the first group of the second typesetting field, the second contact 20 of the fourth array of the second group of the second typesetting box is connected to the second

contact 19 of the first array of the first group of the second type-setting field (set edge 1-4), the third contact 20 of the third array of the second group of the second type-setting field is connected to the third

contact 19 of the first array of the first group of the second typesetting field (set the edge 1-3). The registers 16 of all groups record information about the weights of the corresponding edges of the graph. Weight graph

is entered in the additional binary code, the most significant bits of all the registers 16 are used as service bits (the sign of the edge execution is formed here) and are zeroed before starting work.

Thus, 010 will be recorded in the first register 16 (the service bit and the additional binary code of the number 2), in the second register 16 - 010 in the third - 011, in the fourth - 001.. A unit level impulse signal is input to the initial setup of the device. In this case, all the triggers 12 and 13 go to the zero state, the execution circuits of the keys 14 are opened. At the first input 23 of the initial vertex of the graph, a single-level pulse signal is given. In this case, the first trigger 12 goes into a single state. On the second inlet 24, a single level impulse signal is applied. In this case, the second key 14 closes its executive circuit (the final vertex of the graph is given). A single-level impulse signal is applied to the start input 22. In this case, the synchronization unit 1 starts its operation. The synchronization unit 1 produces single-level pulses at its clock output 25 and output 16. In all registers 16, information is shifted by one bit towards the lower bits, information from the output of adders 6 bitwise from the high bits is written to B- e registers of all groups. Through T pulses., Where T is the resolution of registers 16, the output of block 1 of the 1st bit is 100. By the pulse at output 27 of block 1, the third trigger 12 of the first group will be set to one (the third edge of the graph is reached, third of the top of the graph). Further, the process proceeds in a similar way: one cycle of execution of the graph edge takes place in T cycles (the addition of code in registers 16 with a low-order bit for all registers 16 to the lower-order bits, one is added through the contacts -17 and 18 of the first dial-in field from the trigger output 12).

Simultaneously with the installation of the second trigger 12 of the first group in the unit (i.e. upon reaching the final vertex of the graph), the second trigger 13 of the second group is set to one (the stage of the shortest path begins). A single potential from the output of the trigger 13 is gated with a pulse from the Mo output 28 of the synchronization unit 1 (M 1, ..., B) and propagates through the T T pulses from the output

25 of block 1 through pins 19 and 20 of the second dialed field, from one trigger 13 belonging to the shortest path to another, set them to a single state. The output of the trigger 13, belonging to the initial vertex of the graph, can be input to the stop input of the synchronization unit 1 and be used as a sign of the end of the device operation.

Claims (1)

Invention Formula A device for analyzing the parameters of a graph containing two matrices from B: P elements AND, where B is the number of vertices in the graph, P is the number of edges in the graph, B groups from B shift registers, three groups of B elements And, four groups of B elements UTOi, two groups of B triggers, a group of B consecutive pairs of matrices, a group of B elements NOT, a group of B keys, two typing fields and a synchronization unit, the start input of which is the device start input, the Mth contact (M 1 , ..., P) K-th array (K 1, ..., B), the first group of the first type-setting floor is connected to The first input of the M-th element and the K-th column of the first matrix, the output of which is connected to the M-th input of the K-th element OR of the first group, the output of which is connected to the first input of the K-th element AND of the first group, the output of which is connected to the input of the first the term K-th consecutive adder of the group, the output of which is connected to the input of the higher bit of the B-th shift register of the K-th group, the output of the lower bit of the H-th shift register of the K-th group (H 2 ,,,, Р) is connected to the input of the higher bit (H – 1) of the shift register of the Kth group, the output of the lower bit of the first d an offset of the K-th group is connected to the input of the second addend of the K-th consecutive adder of the group, the K-th input of setting the initial vertex of the device graph is connected to the first input of the K-th element OR of the second group, the output of which is connected to the input of the 1 K-th unit trigger of the first group, the output of which is connected to the K-th contact of the second group of the first type-setting field and to the input of the K-th element of the NOT group whose output is connected to the second input of the K-th element AND of the first group, M-th five the contact of the K-th array of the first group of the second type-setting field is connected to the M-th input of the K-th element OR the third: Group, the output of which is connected to the first input of the K-th element OR of the fourth group, the K-th input of setting the | finite vertex of the graph connected to the control input of the K-th key of the group whose output is connected to the second; Input of the K-th element OR of the fourth troupe, output of the K-th element And the second | Group connected to the first inputs of JBcex elements and the K-th column of the second | the output of the M-th element and the K-th column of the second matrix is connected to the | M-th contact K-g about the array of the second | group of the second type-setting field, also the | output of the synchronization unit pod- | Key to the shift sign inputs | to the right of all the shift registers of all I groups; the first sync output I of the synchronization unit is connected to the third inputs of all elements AND the first I group The second synchronization output of the synchronization unit is connected to the first; Vym inputs of all elements AND the third 366 the group, the initial device installation input is connected to the installation inputs in O of all the triggers of the first and second groups and to the initial installation inputs of all the group keys, characterized in that, in order to reduce hardware costs in determining the shortest path in the graph, the output K-th consecutive group adder is connected to the second input of the K-th element AND the third group, the output of which is connected to the information input of the K-th group key and to the second input of the K-th element OR of the second group, the output of the K-th element OR of the fourth group is connected to the input of the set to 1 K-th trigger of the second group, the output of which is connected to the first input of the K-th element AND of the second group, the second input of which connected to the low-order output of the first shift register of the K-th group, the M-th synchronization output of the synchronization block group is connected to the second inputs of the Mx elements AND of all columns of the first and second matrices. Fig , -) 0SM-k, I. gtI Jq § tJS 8Q to, - CM Fi.Z (t}