SU1705820A1 - Computer - Google Patents

Abstract

The invention relates to computer technology and can be used to build fast Fourier transform processors for digital filters, computers with integrated automaton and digital computers. The aim of the invention is to provide the functional capabilities of the device by performing the operation of dividing kg of plastic numbers. The device contains power units OR 11, 23, 24. triggers 12 .. 22, node 15 of the calculation of the reciprocal, elements AND 14, 16, 20. element NOT, 21, switches 17.18. 19, registers 13.25.26,27,28, 30, multiplier of 29 complex numbers. 2 Il.

Description

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WITH

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The invention relates to computing and can be used to build fast Fourier transform processors, digital filters, computers with complex arithmetic.

The purpose of the invention is to expand the functionality by performing the division of complex numbers.

FIG. 1 shows a functional diagram of a computing device; Fig. 2 is a timing diagram for performing a division operation;

The device contains input 1 of the initial setup, input 2 of the operation code, input 3 of the entry of the operation code, input 4 of clock pulses, second 5 and first b inputs of information recording resolution, first 7, second 8, third 9 and fourth 10 information inputs, first OR element 11, first trigger 12. Fifth register 13, second element AND 14, node 15 for calculating the reciprocal, third element AND 16, switches 17-19, first. D element AND 20, element NOT 21. second trigger 22, second and third elements OR 23 and 24, first to fourth registers 25-28. multiplier 29 of complex numbers, sixth register 30, first 31, second 32 and third 33 information outputs of the device.

The timing diagram (figure 2) illustrates the ratio of the signals at the inputs 4 (1) and 3 (2). at the outputs of the elements OR 23 (3) and 24 (4), at the outputs of the elements AND 14 (5), 16 (6) and 20 (13), at the outputs, triggers 12 (7) and 22 (12) and at the outputs of the first (8), second (9), third (10), and fourth (11) bits of the register (13) when performing the operation of dividing complex numbers.

The device works as follows.

Before starting work, from input 1 a positive polarity impulse arrives, which sets the register 13 and the triggers 12 and 22 0 of the state Log. O. Signal Log. About from the output of the first bit of register 13 sets the switches 17-19 to the state when information from the first inputs arrives at their outputs.

Consider the operation of the device when performing the operation of multiplying complex numbers. At the input 2 of the operation code, the multiplication code (Log, 0) is received, and at the information inputs 7-10 - the real (ReCi ai) and imaginary (ImCi 01) parts of the first number, real (BeCg 32) and imaginary (imC b2) parts the second number.

On the leading edge of signals (level differences from Log.O. to Log. 1) at the inputs

3-6, information is recorded in the trigger 12 (Log. O), registers 25 (ai), 26 (bi), 27 (32) and 28 (b2). Information from the outputs of the registers 2S - 28 is fed to the inputs of the multiplier

29 complex numbers, at the output of which we obtain the product of complex numbers, the real part of which goes to output 31, and imaginary to output 32. The device’s speed when performing the multiply-multiply operation is determined by the multiplier speed 29 of the complex numbers.

Consider the operation of the device when performing the division operation of complex

5 numbers The division code (Log, 1) is sent to the input 2 of the operation code, and the information inputs 7-10 is valid (Red: ai), imaginary (imCi bi), imaginary (imCi bi) and valid (ReCi ai) parts

0 divider Art. On the leading edge of signals at inputs 3-6, which coincide with the leading edge of the first clock pulse, information is recorded in trigger 12 (Log. 1), registers 25 (ai), 26 (bi), 27 (02)

5 and 28 (ai). Information from the outputs of registers 25-28 is fed to the multiplier inputs of 29 complex numbers. On the leading edge of the second clock pulse Log.1, the output of the trigger 12 is recorded for the first time in a row of register 13. Signal Log. 1 from the output of the first bit of register 13 sets the switches 17-19 to the position when information from the second inputs arrives at their outputs. Before starting the third measure on

The 5 outputs of multiplier 29 form multiplication results. The product of the imaginary part of this multiplication (ai2 + bi2) is fed to the input of the node 15 for calculating the reciprocal. Upon the arrival of the front

0 of the front of the third clock pulse, information is shifted in the register 13. During the third clock cycle, the first outputs of the node 15 form a normalized re), which proceeds

0

five

calculation result

-a2:

walks through the switch 19 and enters the input of the register 28. The scaling factor obtained when normalizing the results of calculating the inverse value of (- n). formed at the second output 4) 1 + b

dah node 15 and enters the inputs of the register 30.

On the leading edge of the fourth pulse, information is shifted in register 13. Signal Log. 1 from the output of the third bit of register 13 sets at the output of the element And 16 Log. 1, which sets register 27 to O, and output

element OR 23 - Log. 1. The leading edges of the pulses at the synchronous inputs of the registers 28 and 30 are recording information in these registers. In the fourth cycle, at the inputs to the inputs of the real and imaginary parts of the first number and to the inputs of the real and imaginary parts of the second number of multiplier 29.

01, Oh and. Upon the arrival of the front fronai + b1

This fifth pulse shifts the information in the register 13. The Log.O signal from the inverse output of the fourth bit of the register 13 enters the second inputs of the And 14, 16 elements and sets the Log on their outputs. O. Signal Log. About from the output of the element AND 14 sets the switch 19 to the position when its outputs receive information from the first input. In the fifth cycle, inputs 9 and 10 receive, respectively, real (Re Cr ag) and imaginary (imC2 b2) parts of the divisible C. At the outputs of multiplier 29, multiplication results are formed, which, passing through the switches 17 and 18, arrive at the inputs

31 b1 h “Urf

registers 25 (2- - -) and + ГГ

By

L, 27 (a2) and 28 (L2),

ai + bV N a to the leading edge of the sixth pulse, the information in register 13 is shifted and the Log is written. 1 in the trigger 22, which is fed to the second and third inputs, respectively, of the elements 24, 23 and sets a log on their outputs. 1. On the leading edge of the signals from the outputs of the elements OR 23 and 24, information is recorded in the registers o / a, 2b / S

gi 1 --- x

a1 + bV ai -Nuclear from the outputs of these registers is fed to the inputs of the multiplier 29. In the sixth cycle, at the output of the element 20, a pulse of positive polarity is formed, equal in duration to the interval between the clock pulses. Signal Log. 1 from the output of the element And 20 passes through the element And 11 and sets the trigger 12 and the register 13 to O. Signal Log. About from the output of the first bit of register 13 sets the switches 17 and 18 to the position when their outputs receive information from the first inputs. On the leading edge of the seventh clock pulse, a trigger 22 is recorded in a trigger. O. At the end of the seventh clock cycle at the outputs of the multiplier 29, we obtain the quotient, action / E1E2 4- blD2 I

the necessary part (- 5 - ъ of which post V ъъ 4. n

/ aiD2 -azbi)

al + tf goes to exit 31, and imaginary

V

a + ltf

-Jna output 32. At output 33 we get

tab coefficient of the division result.

The division of the complex numbers in this device is performed in a time of 7 cycles, 5 of which are equal to tons p2 + km + normal to 2 where tp2 is the time of writing to the register;

Tkm - time delay information on

10 switch;

tyM.K is the multiplication time of complex numbers.

The proposed device is effectively used in dividing complex chunks by a complex constant. In this case, the division of the complex numbers by the complex constant is reduced to the operation of multiplying the dividend by the previously calculated reciprocal of the divisor.

20

Claims (1)

Claims A computing device comprising four registers and a multiplier of complex numbers, with the outputs of the first and 25 of the second registers are connected respectively to the inputs of the real and imaginary parts of the first operand of the multiplier complex numbers, the inputs of the real and imaginary parts of the second operand of which 30 are connected to the outputs of the third and fourth registers, respectively; the first and second outputs of the multiplier of complex numbers are connected to the output of the real and imaginary parts of the product of the device, 35 characterized in that. with an extension chain of functionality by performing the division of complex numbers, the device contains the fifth and sixth registers, two triggers, three 40 of the switch, the node for calculating the return value, the elements OR and AND, and the element NOT, and the input of the operation code of the device is connected to the information input of the first trigger, whose power input is connected to the record of the operation code of the device, the initial installation input of which is connected to the first input of the first element OR and the reset input of the second trigger, whose sync input is connected to 50 by the input element NOT, the sync input of the fifth register and the input clock of the device, the first and second inputs of the device recording resolution are connected to the first inputs of the second and third elements OR, respectively, the second inputs of which are connected to the output of the second trigger and the first input of the first element I. second the input of which is connected to the output of the NOT element, the output of the first element AND is connected to the second input of the first element OR, the output of which is connected to the reset inputs of the fifth register and the first trigger, the output of which is the shift input of the fifth register, the output of the fourth bit of which is connected to the information input of the second trigger, the output of the first bit of the fifth register is connected to the control inputs of the first and second switches and the first input of the second element I, the second input of which is connected to the inverse output the third bit of the first register and the first input of the third element And, the second input of which is connected to the output of the second bit of the fifth register, the output of the second element And is connected to the control input of the third switch, the first and The second information inputs of the device are connected to the first information inputs of the first and second switches, respectively, the second information inputs of which are connected to the first and second outputs of the multiplier of the complex numbers, the third information input of the device is connected to the information input third1 jTjnjTj-Lnj-LTL. 2 P Jl its register, the reset input of which is connected to the output of the third element AND, the synchronous input of the sixth register and the third input of the second element OR, whose output is connected to the synchronous inputs of the third and fourth registers, the information input of the fourth register is connected to the output of the third switch, the first information input of which connected to the fourth information input device, the outputs of the first and second switches are connected to the information inputs of the first and second registers, respectively, the clock inputs of which are connected to the output the third OR element, the second output of the multiplier of complex numbers is connected to the input of the reciprocal calculation node, the first and second outputs of which are connected respectively to the second information the input of the third switch and the information input of the sixth register; the first and second outputs of the multiplier of complex numbers are the outputs of the real and imaginary parts of the private device 5 of the sixth register is the output of the device's scaling factor.