SU1520535A1 - Combinatory arrangement - Google Patents

Abstract

The invention relates to the field of automation and computer technology and is intended for use in devices that solve combinatorial problems associated with determining the number of combinations and arrangements. The purpose of the invention is to expand the functionality by determining the number of placements. The device contains registers 1, 4, 19, 22, blocks of subtraction 9, multiplication 17, division 24, counter 11, comparison circuit 12, switch 23, trigger 29, blocks 5, 8, 10, 13, 15, 16, 18, 20 , 25, 27, 30 elements AND, block 31 elements OR, element OR 26. In addition to the function of determining the number of combinations of elements, the proposed device also determines the number of placements. This is achieved by introducing additional blocks into the design: a switch, a trigger, a block of AND elements, a block of OR elements, and an OR element. 1 il.

Description

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JV Yu

ABOUT

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The invention relates to automation and calculate; 1 technique and can be used in devices that solve combinatorial problems related to the calculation of the number of combinations and arrangements.

The aim of the invention is to expand the functionality of the device by determining the number of allocations.

The drawing shows the functional diagram of the device.

The device contains a register 1, a delay element 2, a generator of 3 clock pulses, a register 4, a block of 5 elements AND, a delay element 6 and 7, a block of 8 elements AND, a subtraction block 9, a block of 10 elements And, a counter 11, a comparison circuit 12, block 13 elements AND, element 14, delay, blocks 15 and 16 elements AND, block 17 multiplication, block 18 elements AND, register 19, block 20 elements AND, delay element 21, register 22, switch 23, block 24 dividing , block 25 And elements, element OR 26, block 27 elements And, element 28 delay, trigger 29, block 30 elements And, block 31 elements OR, information inputs 32 and 33, inputs 34 and 35 launch the device to determine the number of layouts and combinations, respectively,

exit 36.

one

The device determines the number C, combinations or A of the arrangements of n elements according to K. The values of n, K before the operation of the device is entered into registers 1 and 4 from inputs 32 and 33. The choice of the task is determined by applying a trigger pulse to one of the inputs 34 and 35 with memorization of the trigger 29 operation mode.

To determine the number of combinations, the trigger 29 is set to one, and the output of the block 20 of the elements AND through the switch 23. is connected to the input of the block 24 and a zero code is formed at the other output of the switch. Block 30 of the elements AND appears open to transfer information from block 27 of the elements AND to block 31 of the elements OR.

Running the signal, having passed through the element CMM 26, produces the initial

through element 2, the delay starts the generator 3.

The next i-pulse from the generator output goes to the counting input of the sc: etchik 11, increasing its content by one and is set to state i.

At the same time the clock pulse is fed to the inputs of the elements 6 and 7 of the delay. The output signal from element 6, delayed by the response time of counter 11, is fed to the inputs of blocks 5, 8, 10, and 16 elements And and the input of element 14 delay. By this signal, the code of the number K is fed from register 4 through the block 8 elements AND to the input of the comparison circuit 12, to the second input of which the current state code of the counter 11 is received through the block 16 elements I. If the compared numbers are equal, then the comparison circuit generates a signal entering the stop input of the generator 3, prohibits the generation of clock pulses. one

If the numbers are not equal, then the generator

after a time determined by the period of the following clock pulses, it forms the next pulse, and the operation of the device continues.

Let the numbers are not equal. Then the code of the number from register 1 goes through block 5 of the elements AND to the input of block 9 of the subtraction, to the second input of which the previous counter state code is stored, stored in register 19. Thus, the outputs of the block of subtraction form the difference code n- ( i-1), Ilo, by the expiration of the time determined by delay element 7, the passage of the state code of its output counter 11c through the block 15 of elements AND to the input of register 19, where it is stored, is allowed. At the i-th cycle, the pulse delayed by element 14, entering the control inputs of block 13 and 18 elements AND, ensures that the code n of the number n- (i-1) and the register output 22

n - (1-1)

setting the subtraction unit 9, the multiplication unit 17, the division unit 24, the counter 11 and the register 19 to the zero state, and the register 22 is written 1 in binary code. Same signal

equal to the number of C J combinations. This number is fed to the inputs of block 17 multiplication. The multiplier performs the calculation of the product (n- (i-1)) i

At the same time, the pulse from the output of the delay element 14 is fed to the input of the delay element 21, where it is delayed by the response time of the block um-. The signal from the output of the delay element 21 is fed to the input of the delay element 28, as well as to the control inputs of the blocks 20 and 25 of the elements I. Thus, the passage to the inputs of the division unit 24 from the output of the multiplication unit 17 through the switch 23 of the Cn code (n- (il), and from the output of the counter 11 - the code of the number i. The quotient from the division

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t5 pa is connected to the information input of the first block of AND elements, the output of which is connected to the input of the decrementing subtracting unit, the output of the subtraction unit is connected to the information input of the second block, the AND element whose output is connected to the first information input of the multiplication unit, the output of the multiplication unit is connected to the information oHHbw input of the third block of elements

20

| enters via blocks 27, 30 and 31 to register 22, where it is stored until the next clock cycle.

At the Kth cycle, at the output of the counter 11, a state code corresponding to the K number is formed, as a result of which the comparison circuit 12 will generate a signal, 25 And, the counter output is connected to the information input to the stop input by the generation inputs of the fourth, fifth

and the sixth block of elements And, the output of the fourth block of elements And is connected to the information input of the third 30 register, the output of which is connected to the information input of the seventh block of elements And, the output of which is connected to the input of the subtracted subtraction unit, the output of the fifth block of elements And sub- - it is connected to the input of the divider of the dividing unit, the output of which is connected to the information input of the eighth block of elements I, the output of the fourth register is the output of the device and the sub head 26, sets the blocks of the device to the information input at nine to the initial state and through the element block of elements I, the output of which 2 delays triggers the generator of the ryo connected to the second information

the input of the multiplication unit, the output of the second register is connected to the information input 5 of the tenth block of AND blocks,

the outputs of the sixth and tenth blocks of elements I are connected to the inputs of the comparison circuit, the input of the first delay element is connected to the inputs of the initial installation of the subtraction unit, multiplication unit, division block, counter, At the Kth cycle at the output of the third and fourth registers, you a state code is generated corresponding to the number K, as a result of which the clock pulses are generated by the signal from the comparison circuit 12. At the same time, in the Kth cycle, all actions leading to the production of

of torus 3. At the same time, on the kth clock cycle all the actions described for the clock cycle will be executed, and, therefore, in register 22 the product will be accumulated

i n- (i-l) k

I

tsl 1

which can be removed at exit 36.

To determine the number of arrangements, trigger 29 is set to the zero state. In this case, the trigger signal also passes through the element

3. Further operation of the device is analogous to that described, except that the result of the multiplication Cn (n- (i-1)) comes from the output of multiplication unit 17 through blocks 20, 23 and 31 to the input of register 22, where it is recorded and stored until the next clock cycle.

50

55

the stroke of the first delay element is connected to the starting input of the clock pulse generator, the output of which is connected to the counter input of the counter and to the inputs of the second and third delay elements, the output of the second delay element is connected to the control input (n- (il)) L, recording the result in register 22.

Claims (1)

Invention Formula A combinatorial device containing four registers, a subtraction unit, a multiplication unit, a division block, a counter, a comparison circuit, ten blocks 0 I elements, a clock pulse generator and six delay elements, the inputs of the first and second registers being information inputs of the device, the output of the first register 5 pa connected to the information input of the first block of I elements, the output of which is connected to the input of the decrementing subtraction block, output the subtraction unit is connected to the information input of the second unit, the element I, the output of which is connected to the first information input of the multiplication unit, the output of the multiplication unit is connected to the information oHbw input of the third unit ntov 0 5 And, the output of the counter is connected to the information inputs of the fourth and fifth the outputs of the sixth and tenth blocks of the AND elements are connected to the inputs of the comparison circuit, the input of the first delay element is connected to the inputs of the initial setup of the subtraction unit, multiplication unit, division unit, counter, third and fourth registers, five the stroke of the first delay element is connected to the starting input of the clock generator, the output of which is connected to the counter input of the counter and to the inputs of the second and third delay elements, the output of the second delay element is connected to the control inputs of the first, sixth, seventh and tenth blocks of the And elements and the input of the fourth delay element, the output of the third delay element is connected to the control input of the fourth block of elements And, the output of the fourth delay element - to the control inputs of the second and ninth blocks of the element in and to the input of the fifth delay element, the output of the fifth delay element is connected to the control inputs of the third and 1 that block, the AND elements to the input of the delay delay element, the output of which is connected to the control input of the eighth block of the AND elements, the output of the comparison circuit - to the clock pulse generator stop input, characterized in that, in order to expand the functional capabilities of the device by determining the number of arrangements, it contains a switch, a trigger, the eleventh block of elements I., a block of elements OR and the OR element, the output of the third block of AND elements is connected to the information input of the switch, the switch outputs are connected respectively to the input of the divisible division block and to the first input of the OR block, the output of the eighth AND block of the elements is connected to the information input of the eleventh AND block of output elements to the second input of the block of elements OR, the output of the block of elements OR is connected to the information input of the fourth register, the single and zero inputs of the trigger are connected to the inputs of the element OR and are The device start inputs for determining the number of combinations and arrangements, respectively, the output of the trigger is connected to the control inputs of the switch and the eleventh block of AND elements, the output of the OR element is connected to the input of the first delay element.