SU1490711A1 - Device for computing number of pulses per time unit - Google Patents

Abstract

The invention relates to a pulse technique and can be used to count the number of pulses per unit of time. The purpose of the invention is to expand the frequency range. The device contains reversible counters 4 and 12, the elements OR 7 and 8, the element AND 6, the shift register 3, the driver 5, the decoder 9, the inverter 10 and the delay element 11. The counter 12 forms the code of the number of pulses per unit time, which is determined by the product period of clock pulses on the bus 2 to the width of the shift register 3. The code in the counter 12 increases when the input pulses arrive and decreases when they are absent due to the pulses from the output of the imager 5. 2 Il.

Description

1

The invention relates to a pulse technique and can be used to record the flow of micrometeorites, the FLOW of elementary particles, in microbiological studies, in digital systems of automatic control and control.

The purpose of the invention is to expand the frequency range.

Figure 1 shows the structural scheme of the device for counting the number of pulses per unit of time; 2 shows timing diagrams for his work.

A device for counting the number of pulses per unit of time contains an input signal bus 1, a clock signal bus 2, a shift register 3, a reverse counter 4 pulses, a shaper 5, an AND 6 element, a first 7 and a second 8 OR elements, a decoder 9, an inverter 10, a delay element 11, and an additional reversible counter 12 whose output is the output 13 of the device. The input signal bus 1 is connected to the addition inputs of reversible counters 4 and 12, the information input of the shift register 3 and the input of the delay element 11, the output of which is connected to the first input of the AND 6 element, the output of which is connected to the inverse dynamic clock input of the shift register 3 and forward dynamic a clock input for starting the imager 5, the resolution input and the output of which are connected respectively to the output of the shift register 3 and subtracting the input of the additional reversing counter 12, the second input of the element I 6 with the output of the first element OR 7, the first input of which is connected to the bus 2 of the clock signal, which is connected to the first input of the second element OR 8, the second input and output of which are connected respectively to the output of the inverter 10 and the subtractive input of the reversing counter 4, the output of which is connected to the decoder 9, the output of which is connected to the input of the inverter 10 and the second to the input of the first element SH 7.

The device works as follows.

In the initial state at the output of the decoder 9 there is a logical zero value, which is inverted by the inertor 10 and fed to

d d

0

five

the input of the first logical element OR 8, preventing the arrival of clock pulses through the first logical element OR 8 at the subtracting input of counter 4. The clock pulses through the logical element OR 7 and the logical element AND 6 arrive at the clock input of the shift register 3 and the input of the racer 5. On arrival the pulse on the bus 1 input signal to the summing input of the counter 4 at the output of the decoder 9 is set to a single value, which is inverted by the inverter 10 and, arriving at the first input of the logic element OR 8, allows ktovm pulses supplied to the subtracting input of the counter 4. At the same time a signal is input to a summing input of the counter 12 and the input of the shift register 3. The value of logic one from the output of decoder 9 is supplied to input of the OR logic element 7, the other input of which is connected bus 2 clock pulses. Thus, the receipt of clock pulses on the logical element AND 6 is blocked, at the first input of which the value 1 is set.

 At the other input of the logic element 6, the input signal delayed by the response time of the counter 4 and the decoder 9 is received. From the output of the logical element And 6 it is fed to the input of the shift shift register 3 and the first input of the imaging unit 5.

Thus, the information in the shift register 3 is shifted by each input pulse and then by clock pulses when a zero signal appears at the outputs of counter 4 and decoder 9. The signal from the output of the shift register 3 is fed to the input of the generator 5. In the case when a shift pulse arrives at one input of the shaper 5, and a single signal from the output of the shift register 3 arrives at the same input of the shaper 5, the shaper 5 generates a short pulse arriving at the subtracting input of the counter 12 .

Thus, at output 13, the numerical value of the pulses received via the bus 1 of the input signal and recorded in the shift register 3, i.e. come in unit time. The value of the unit of time is determined by multiplying the period of the clock pulses by the width of the shift register.

Formula

514907

the invention

A device for counting the number of pulses per unit of time, comprising an input signal bus, a clock signal bus, a shift register, a reversible pulse counter, a driver, and an AND element, characterized in that, in order to expand the frequency range, the first and second elements are entered into it The RSHI, the decoder, the inverter, the delay element and the additional reversible counter, the output of which is the output of the device, the input signal bus is connected to the inputs of the addition of the reversible counters, the information input of the shift register pa and the input of delay element whose output is connected to a first input of AND gate, the output

11 6

which is connected to an inverse dynamic clock input of the shift register and a forward dynamic clock input of the driver, the resolution input and output of which are connected respectively to the output of the shift register and the subtractive input of the additional reversible counter, the second input of the AND element is connected to the output of the first OR element, the first input of which connected to the bus clock signal, which is connected to the first input of the second element OR, the second input and output of which are connected respectively to the investment code Operations and subtraction input of down counter whose output is connected to a decoder whose output is connected to the inverter input and a second input of the first OR element.

Claims (1)

Claim A device for counting the number of pulses per time unit containing an input signal bus, a clock signal bus, a shift register, a reversible pulse counter, a shaper and an And element, characterized in that, in order to expand the frequency range, the first and second OR elements, a decoder, an inverter, a delay element and an additional reverse counter, the output of which is the output of the device, the input signal bus is connected to the inputs of the addition of the reverse counters, the information input of the shift reg istra and the input of the delay element, the output of which is connected ₂ 0 with the first input of the And element, the output of which is connected to the inverse dynamic clock input of the shift register and the direct dynamic clock input of the start of the driver, the enable input and output of which are connected respectively to the output of the shift register and the subtracting input of the additional a reverse counter, the second input of the AND element is connected to the output of the first OR element, the first input of which is connected to the clock bus, which is connected to the first input of an OR element, the second input and output of which are connected respectively to the inverter output and the subtracting input of a reversible counter, the output of which is connected to a decoder, the output of which is connected to the inverter input and the second input of the first OR element. ΓτπππτπππππππππΓίΓΐ / 12-2 12-3 r ~ L_r pl_gi 1_PL FIG. 2