SU1580561A1 - Device for shaping residue from arbitrary module - Google Patents

Abstract

The invention relates to computing and can be used in digital computing devices. The device contains the first and second counters, the register element AND, the first element OR, the first unit for determining the multiplicity of numbers, the first prohibition element and the delay element. In order to increase speed, it contains the second OR element, the third and fourth counters, the second prohibition element, the switch and the second number multiplicity determination unit. 1 il.

Description

The invention relates to computing and can be used in digital computing devices.

The aim of the invention is to increase speed.

The drawing shows a diagram of a device for forming a remainder in an arbitrary modulus of a number.

The device contains the first 1 and second 2 counters, register 3, the element AND 4, the first element OR 5, the first block 6 for determining the multiplicity of numbers, the first element 7 of the ban, the delay element 8, the second element OR 9, the third account

Chik 10, the second element 11 of the ban, the switch 12, the fourth counter 13 and the second block 14 determine the multiplicity of numbers.

The essence of the invention is that the number Ak is divided by the magnitude of the modulus P; and then it is determined whether the fractional part of the quotient is zero. If the result of dividing contains a fractional part that is different from zero, then simultaneously the magnitude of the Ak number is reduced and increased by one and the results are divided by P. If the numbers containing fractional parts other than zero are obtained again, then again the sum is increased by one, and the difference Ak-1 is reduced by one and the results are also divided by P; etc. until the fractional part of the private

0

five

five

0

five

from dividing increased or decreased A by PJ will not be zero. If the fractional part of the quotient of dividing the increased A by P (is equal to zero, then, r0, where rQ is the number of increases in the number Ak, if the reduced A., then.

The introduction of the third counter ensures the formation of a value

-k

A A ". The introduction of the fourth counter provides the recording of the number Ak and the formation of the values Ats + 1, Ak + 2,. . . , AK + rb.

The second unit for determining the multiplicity of numbers provides a check for the multiplicity of numbers AK + i to the module P-. The second OR element is intended for combining the output signals of the units for determining the multiplicity of numbers. The switch is designed to issue a residual code through it, depending on which counter (second or third) it is formed on.

Blocks 6 and 14, which determine the multiplicity of numbers, as well as in the known device, are implemented on programmable logic arrays and realize the function of determining the multiplicity of numbers arriving at their inputs. They are discrete devices whose operation algorithm is described by bracket forms of logical functions, and the speed is determined by the speed of the AND and OR elements included in their composition.

The device works as follows.

51

The module P, but which needs to form the remainder of a given number of ACs, is defined by a parallel binary code supplied to the inputs of the parallel register register 3 and the counter 10. This parallel binary code is numerically equal to the value of the module being defined. The inputs of the parallel recording of counters 1 and 13 are affected by the binary code of the number AK. The start signal has reset counter 2, switches switch 12 to its initial state, in which none of its inputs is switched to the output, and also records the binary code of the number Ac in counters 1 and 13 and the binary code of the module in register 3 and counter 10 As a result, at the outputs of counters 1 and 13, parallel binary codes of the ones and zeros of the number Ak are formed, and at the outputs of the register 3 and the counter 10 are parallel binary codes of the module. These codes from the outputs of counters 1 and I and the register 3 are fed to the inputs of blocks 6 and 14 for determining the multiplicity of numbers. Simultaneously, the start signal through the first element OR 5 is fed to the input of the element 8 delay. If number A is divided by modulus P; All in all, unit potentials appear on the outputs of blocks 6 and 14 of the multiplicity determination, and the unit potential affects the control input of prohibition element 7 and the first input of element 5. And signals from the outputs of blocks 6 and The 14 definitions of the multiplicity of numbers also arrive at the prohibition element i1, which, under the action of the unit potential arriving at its control input, opens, therefore the unit potential only from the output of the number multiplicity determination unit 6 enters the second control the switch 12, under the influence of which the output of the counter 2 is switched to the output of the device.

At the same time, the second inputs of the And 5 element and the prohibition element 7 from the delay element 8, the delay value equal to the duration of transient processes in counter 1 (register 3) and in unit 6 for determining the multiplicity of numbers, a single pulse of the trigger signal is received, due to which - element 4 is melting, the signal from the output of which indicates that at the output of counter 2 there was formed os805616

tatok ak OtooR. The residue caddy from the outputs of counter 2 through switch | 2 is removed at the output of the device. If the number A ,, is not a multiple of the module

P-, then at the outputs of blsg 6 and 4, zero potentials remain, therefore, with the appearance of a pulse at the combined second inputs of the element 11 4 q (O barring element 7 from the output of delay element 8, cp blocks the barring element 7, since its control input zero potential comes from the output of the second element OR 9. Nm) 5 pulses from the output of the prohibition element 7

the unit is recorded in counter 2, the unit is subtracted from the soder / bothersome counters 1 and 10, and the unit is added to the contents of counter 13. One20 temporarily through the OR element imposes to the input of the delay element 8. Now block 6 checks the multiplicity of the number, l block 14 - the number of A +1 module. If pi

25 one of them is not a multiple of the module, then again the output of the element OR 9 remains zero potential, therefore the pulse from the output of the delay element 8 causes the prohibition element 7 to trip,

The 30 pulse from its output ensures that the second unit is recorded in counters 2 and 13 and the second unit is subtracted from the contents of counters 1 and 10. Then a check is made for the multiplicity

js of numbers Ak - 2 and A), + 2 modulo P.

The operation of the device in this mode continues until one

of the numbers Ai-g or A + g will not

multiple of the module. Suppose AK, + r OiucidPj.

40 In this case, at the output of unit 14, Vits has a single signal that, through the element OR 9, goes to the first inputs of the elements AND 4 and prohibition 7. Therefore, the signal from the output of element 8

45 the delay arriving at their second inputs ensures the operation of the element 4, at the output of which a signal appears indicating the end of the process of formation of the remainder. The remainder of the number A by

50 selected module, numerically equal

P, -g, from the output of the counter 10 through the switch 12, triggered by a control signal received at its first input through the prohibition element 55 from the output of block 14, goes to the output of the device and remains at its outputs until until the information inputs of the device do not receive the following number A, from

which is necessary to form a residue modulo G,.

If A -r OmodP, then a signal of a logical unit appears at the output of block 6, therefore a control signal appears at the second input of switch 12, the information outputs of counter 2 are connected to the information outputs of the device. The remainder of. the numbers a to k on the selected module P; , numerically equal to r, is fed to the output of the device.

If the value of the module is even and ak P | / 2, then the logical unit signals at the outputs of blocks 6 and 1A appear simultaneously, but since the propelling element 11 is j interrupted by the action of the signal coming to its control input, the contents of the device will switch counter 2. When forming the remainder of the number of AK +, modulo P: the operation of the elements and units of the device is carried out similarly.

ten

15

the delay, the output of which is connected to the information input of the first prohibition element, the control input of which is connected to the first input of the element I, the second input and output of which are connected to the output of the delay element and to the output of the end of the device, respectively, characterized in that, in order to improve performance , it contains the second element OR, the third and fourth counters, the second prohibition element, the switch and the second unit for determining the multiplicity of numbers, the outputs of the fourth counter and register are connected respectively the first and second inputs of the second multiplicity determination unit, the information input of the fourth counter is combined with the information input of the first counter, the summing input of the fourth counter is connected to the subtractive input of the first counter, the write enable input of the fourth counter is connected to the device start input, the output of the first number multiplicity block connected to the first input of the second element OR, to the control input of the second device for the formation of the remaining 30 prohibition element, the output of which

20

25

Claims (1)

Invention Formula ka arbitrary module of the number containing the first and second counters, the register, the AND element, the first OR element, the first number multiplicity determination unit, the first prohibition element and the delay element, the number inputs and the device module are connected respectively to the information inputs of the first counter and register , whose recording enable inputs and the reset input of the second counter are connected to the device start input, the summing input of the second counter is connected to the subtractive input of the first counter, to the output of the first prohibition element and the first input of the first element OR, the outputs of the first counter and the register are connected respectively to the first and second inputs of the first number multiplicity determination unit; the second input and output of the first element OR are connected respectively to the device start input and to the input of the element connected to the first control input of the switch, the second control input of which is connected to the control input of the second prohibition element, the output of the second number multiplication unit is connected to the information input of the second prohibition element and to the second input of the second OR element, the output of which is connected to the control input the first prohibition element, the device start input is connected to the switch lock input and the third counter recording enable input, the information input of which is connected to the information input reg Stra, subtracting input of the third counter is connected to the output of the first barring member, the outputs of the second and third counters are connected to the first ring and the secondary information switch inputs, respectively, the output of which is a data output device.