SU611252A1 - Long-time storage - Google Patents

Description

one

The invention relates to computing, in particular to memory-storage devices of electronic computers.

Long-term memory devices are known for reproducing a function, one of which contains an input register, all of which are connected to the inputs of the deitfrarator, shi (} rators and switching fields connected to the outputs of the encoders. The known device has a low real-time performance when information is input. devices directly from the transform; teli analog-code. Closest to

i an invention is a device containing an input register, the outputs of which are connected to the inputs of the decoder, chi (} chrator, the same-named inputs are connected to the corresponding outputs of the decoder, and the outputs are connected to the inputs of the corresponding OR elements, and the first control bus connected to the input the input of the input register, to the second input of which is connected the information

tire. This known device has the same speed when working in real time because of the impossibility of generating control actions for the executive body of the control system until the complete accumulation of the hopping information.

The aim of the invention is to increase speed. In the proposed device, this is achieved by the fact that it contains control keys, a delay unit, a counter, and a second and third control bus, wherein the first inputs of the control keys and the input of the delay unit are connected to the second control bus, the second inputs of the control keys, except the first, connected to the corresponding outputs of the decoder, the output of the delay unit is connected to the third input of the input register, and the outputs of the control keys are connected to the control input; the house of the corresponding encoder, the outputs of the OR elements are connected to one e counter inputs, the other inputs of which are connected to the first and third control buses

The drawing shows a block diagram of the proposed device.

It grows from the input register 1, the decoder 2, the encoder 3, the control keys 4, the elements OR 5, the counting b, the delay block 7, the information bus 8, the first control bus 9, the second control bus 10 and the third control bus 11.

In the initial state, in the first discharge of the first register 1, the unit is written down, and in the remaining bits, zeros. The control keys 4 are full on the triggers, the first of which is set to one, and the rest are set to zero. Counter 6 is set to zero.

To play the function, rt cycles are performed, each consisting of two cycles. By the beginning of each 3rd cycle, the value of the i-th bit of the argument enters via information bus 8. Bus 9 receives a control signal that shifts the information in the input repistor 1 and in counter 6. As a result, in C i +1) -I, the input register 1 register is recorded, the 4 minor digits of the input register 1 are formed the code defined by the bits of the operand that had accumulated by that time. A second code is generated at the outputs of the second time. The code is canceled by the input register 1 in the second clock. In the second cycle, the control signal is received, which code from the outputs of the elements OR 5 is summed with the code found in the counter 6. This completes the pick point playback function.

After this J | / 2 EIKLOV, a control signal arrives on the Yu bus, the non-Rio of which is C / 2 times longer than the time spent on a single cycle. By this control signal, the first Trigger is set to the zero state, and one of the remaining ones is set to the bare one (this is determined by which of the dual buses 2 have a single signal). By the same control in the subject of the signal in time determined by block 7, the input register 1 is set to its original position. Then another ff / 2 ENC. As a result of the execution of n nicks in the counter b, a code is formed, the value of which is equal to the value of the function for the given value of the argument.

Thus, in the proposed device, the value of the reproduced function is calculated over m cycles, and the most significant bit of this value (in the redundant code), which carries much information about the magnitude of the control action for the actuator of the control system, is calculated in the first cycle, the process of forming the complete result code is combined with the process of inputting the argument bits. .It causes affective use. The proposed device in process control systems in real time. In addition, the proposed device allows reducing hardware costs by 2.5 times.

Invention Formula

A long-term memory device for reproducing functions containing an input register, the outputs of which are connected to the inputs of the decoder, extensions, the like inputs of which are connected to the corresponding decoder codes, and the outputs of the corresponding OR inputs, and the first control bus connected to the nepBbiM input of the input register An information bus is connected to the second input, characterized in that, with a speed increase of the device, it contains control keys, an hold block, and a counter. to both the second and third control buses, the first B7, control 1 Kzshnkh Klyuks and the input of the delay unit are connected to the control bus, the second inputs of the control keys, except for the first one, are connected to the corresponding outputs of the Fail decoder, the output of the delay unit is connected to the third input of the input register, and the outputs of the control keys are connected with the control input of the corresponding encoder, the outputs of the OR elements are connected to one of the counter inputs, and the inputs of which are connected to the third control bus.