SU682890A1 - Communication processor - Google Patents

Description

The goal is achieved by the fact that a switch and a unit of modulo-two adders are inserted into the device. First entry

and the output of the block of adders according to mod. two

connected respectively to the output of the general purpose register unit and the first input of the switch, the output of which is connected to the third input of the result register. The second inputs of the modulo two adders and the switch are connected to the first output of the upper bits of the intermediate result register, the second output of the higher bits of which is connected to the third input of the switch, and the output of the lower bits with the input of the lower bits of the result register.

The drawing shows the block diagram of the device.

It contains a control block 1, a permanent memory, a block 2, an arithmetic block 3, an operative memory, a block 4, a block 5 of the register registers, its purpose, counter 6 shifts, decoder 7 zero of the counter shifts, register 8 intermediate result, register 9 results, switch 10, block AND modulo adders.

The device works in the following way.

The processing of information in the drying device is performed in accordance with the program, which is stored as a sequence of commands in a persistent storage unit 2.

The specified sequence of commands is executed by the control unit 1, which generates the current address and commands it to the input of block 2, from where the selected command arrives at the input of block 1. Here it is decrypted and converted to control signals that come from the outputs of block 1 to the inputs of the operational memory, its block 4, block 5, registers 8 and 9, counter 6 shifts and arithmetic block 3.

Forwarding operations, logical and arithmetic operations are performed by the arithmetic unit 3 on the operands that come from block 4 or 5. The result of the operation goes to the input of register 9, from which it is then sent either to the pa input of block 4 or to the input of block 5. When performing transition operations, the transition address goes to block 1 from block 3. When performing shift operations, operands from block 5 go to register 9 through block 3, and then write to register 8 from the output of the last. Then, the operand indicating the number of shifts is written a block of 5 to 6. The counter registers 8 and 9 form a reversible shift register by the fact that the contents of register 8, the intermediate result may be transmitted to the counting input of register 9 result shifted right or left by one bit. Simultaneously with the execution of the shift, one discharge of counter 6 is reduced to a unit. When the counter reaches 6 zero, the decoder 7 issues a signal about the end. Shifts to input 1, coders. p.rekr.ashchaet. vypolitsie. Shifts and sends the result.-of. register 9 in block 5 .., -: ... .--

The formation of the address is generated in block 4. It is carried out in an arithmetic unit 3. The address of the block. From the output of the arithmetic unit 3, through register 9 is written to register 8, from the output of which is output to block 4 .....

In order to execute the encoding and decoding programs of the cyclic codes in the device is provided. operations division of polynomials. When performing this operation, an information sequence is selected from one of the registers of block 5 specified in the command, which .... Through the arithmetic unit 3 is placed first in the register: 9, and then rewritten into register 8. Then it is selected from the other register of block 5 the second operand, the leading / digits of which determine the generating polynomial g (X) of the cyclic code used, and the lower s- / digits determine the number of .. shiftings when performing the operation of the delpe of polynomials, where s is the register size of the block 5, register 9 and reg Istra-.8. If the degree of the polynomial g (X) is less than /, the polynomial is located in the higher bits, and the unused bits are filled with zeros. Older / bit from block output. 5 is fed to the input of block 11 of adders. Modulo two, and the lower s- / bits of the block: .5. Are written to the 6-shift counter. - ..

The input of block 11c of the output of the higher, bits of register 8 receives 1 senior bits of the information sequence, which are also fed to the input of the switch 10. The sum of. module two generating polynomial g (X) and higher bits of the information sequence from the output of block 11 is fed to switch 10. Then the division of polynomials is actually performed, as usual division, in which the subtraction procedure is replaced by addition modulo two, and the subtraction criterion is The quotient reduced by the more subtracted is replaced by checking the equality of the unit of the highest bit of the partial decreasing, which is in the intermediate result register. Therefore, depending on the value. The first bit of register 8, supplied from the high-order output of the last bit to the input of switch 10, is transferred to the high-order bits of register 9 with shift ig by one bit to the left or sum modulo two polynomials g (X ) and the higher bits of the informational information of the investigator, if the value of the higher bit is a long one, or the highest bits of the information sequence, if the value of the higher bit is zero. Thereafter, the contents of register 9 are transferred to register 8, and the division cycle ends.

After each division cycle, the value of counter 6 decreases by one. According to the signal from the output of the decoder 7, the division of polynomials is colored, eats. The remainder of division from register 9 is sent to block 5 in place of the original information sequence.

If the length of the information sequence is greater than S, then its remaining part is located in block 4 and. after each (s- /) shift, the division of the polynomials ceases, at the lower bits of the register of block 5, in which the intermediate remainder is placed, the next part of the information sequence is added, and the division of the polynomials is resurrected. is.

Thus, the device provides real-time communication with data channels.

Claims (2)

Invention Formula The communication processor containing the control unit, the first input and. the output of which is connected respectively to the output and input of the command persistent storage, and the second input and output are connected respectively to the first output and input of the arithmetic, block, general purpose register-registers connected by the first input to the third output of the control unit, the fourth output of which is connected to the first input of the operational storage unit, the result register, the output of which is connected to the second inputs of the block of general purpose registers, the output of which is connected to the second input is arithmetic unit and the first input of the shift counter, the operational storage unit connected by the output to the third input of the arithmetic unit, the first input of the intermediate result register, the decoder n. t shift counter, connected by the input and output respectively to the output of the shift counter and the third input of the control unit , the fifth, sixth and seventh outputs of which are connected respectively to the second inputs of the shift counter and intermediate result register and the first input of the result register connected by the second input to the second output of the arithmetic unit, the counting input of the result register is connected to the first output of the intermediate result register, the second output of which is connected to the address input of the operational storage unit, so that, in order to increase the speed of the device, A switch and a block of adders modulo two are entered into it, the first input and the output of the block of modulo adders are connected respectively to the output of the block of general-purpose registers and the first input of the switch, the output of which is connected to three With the input of the result register, the second inputs of the modulo two adders and the switch are connected to the first output of the upper bits of the intermediate result register, the second output of the higher bits of which is connected to the third input of the switch, and the output of the lower bits is the result . Information sources, taken into account in the examination of L. USSR Certificate of USSR № 404087, cl. G 06F 9/00, 1971. .... 2. Fl ores A. Organization of computers. M., “Mir, 1972, section 9.4 (prototype).