SU1644137A1 - Device for random repmutation searching - Google Patents

Description

(21) 4677694/24

(22) 04/11/89

(46) 04.23.91. Pitchfork 1 15

(72) K.M. Abdrashitov and A.A.Garmonov

(53) 681.31 (088.8)

(56) USSR Author's Certificate p 1269128, cl. G 06 F 7/58, 1985.

(54) DEVICE FOR RANDOM QUANTIFICATION

(57) The invention relates to automation and computing. The purpose of the invention is to improve the accuracy of equalization of probabilities and decorrelation of permutations. The device contains groups of blocks of BANKS 5, 7, groups of blocks of elements AND 4, 11, groups of blocks of elements OR 6, 12, element OR 10, group of registers 9 of memory, generator 1 of clock pulses, generator 2 of a random code and decoder 3. Each the subsequent permutation is obtained from the previous one by cyclic shift in two cycles simultaneously. In this case, the entire set of information registers is randomly divided into two groups. 1 il.

This invention relates to automation and computing.

The aim of the invention is to improve the accuracy of the likelihood and decorrelation of permutations.

The drawing shows a block diagram of a device for six swappable elements.

The device contains a generator of 1 clock pulses, a generator 2 of a random code, a decoder 3, a group of blocks of elements AND 4-4g (groups of blocks of elements BANKS 5 - 56, a group of blocks of elements OR 6-65, a group of blocks of elements BANNER 7-7f, outputs of elements of permutations 8 - 86 devices, a group of registers 9, - 96 memory, an element OR 10, a group of blocks of elements AND 11 - 11 $ -, a group of blocks of elements OR 12 1 - 12§-.

The device works as follows.

Let the following sequence of binary codes be fixed in positions 1-6: 1, 2, 3, 4, 5, 6.

.A randomly selected cyclic shift number k (e.g.

1 number k 3). This leads to a shift of binary codes from the third position to the fourth, from the fourth to the fifth, from the fifth to the sixth, from the sixth to the third,

At the same time, this leads to a shift of binary codes from the first position to the second, from the second to the first.

As a result, the following sequence of binary codes will be fixed in positions 1-6: 2, 1, 6, 3, 4, 5.

At k 5, there is a cyclic shift of binary codes from the fifth position to the sixth, from the sixth to the fifth and simultaneously from the first to the second, from the second to the third, from the third to the fourth

twirling, from fourth to first.

with&

and

4b

oo j

As a result, n positions 1-6 will fix the following sequence of binary codes: 3f 2, 1, 6, 5, 4.

With k 6, at positions 1-6, the following sequence of binary codes will be locked: 5, 3, 2, 1, 6, 4.

At k 2 positions 1-6, the following sequence will be fixed: 5, 4, 3, 2, 1, 6.

With k 1 in positions 1-6, the following sequence will be fixed: 6,5,4,3,2,1.

In the initial state, registers 9-9 are written (binary codes of numbers 1-6 are written respectively. The random binary code generated by generator 2 is converted by decoder 3 into a random unitary code. Suppose that this single signal is wired at the third output of the decoder (k 3). This single signal enters the first input of the AND 4 $ element and closes the BAN 5 and 7 element. This single signal through the OR 10 element simultaneously arrives at the first input of the AND 4 element,) and enters the clock inputs of the 9, register registers 9 ,, causes soda shift Římov registers: from 9 to 92, from 9 to 9g, of 93 to 94, from 94 to 9, of a 9S 9b and 9b in Ud. As a result, at outputs 8, - Bg devices receive the following sequence of binary codes: 2, 1, 6, 3, 4, 5.

Further suppose the following. single signal by wils at the second output of the decoder (k 2). This single signal arrives at the second input of the element AND 114 and the first input of the element And 42, it also closes the elements BANCH 7 and 5 p of the input to their inverse inputs. Through the element OR 10, the same signal appears at the first input of the element AND 4 and at the synchronizing inputs of memory registers 9-9g, causing the contents of the registers to shift from 9g to 9h, from 9 to $ 9, from 9G to Uy, from 9 to 96, out of 9Ј 9. Through the elements AND 11,, OR 12 ,,, And 4, the information from the output of register 9 is overwritten into it and goes to output 8. As a result, at the outputs 8, - 8g, the following sequence of binary codes is obtained: 2, 5, 1, 6, 3, 4..

Further, let us assume that the next single signal by wils is at the sixth output of the decoder (k 6). This single signal closes the BANKS 7 g- and 5y elements, arrives at the first input of the element AND 46, through the element OR 10 the same single signal enters the first input of the element AND 4 at the synchronization inputs of memory registers H - 9g, causing the registers to shift from 9 b9a, from 91 to Uj, and 9 h., From 9 $ to 9, from 9 $ to 9. Through the elements AND 4, OR the database information from the output of register 9g is rewritten into it and arrives at output 8g. As a result, at the outputs 8 {- 8g, the following sequence of binary codes is obtained: 3, 2, 5, 1, 6, 4.

Let the next single signal for vils on the first output of the decoder (k 1). This signal arrives at the first input of the AND 4 element and the synchronizing inputs of memory registers 94-9g, causing a shift in the contents of the registers from 9 to 9, from 92 to 9, from 9 j to 94, from 9 to 9, from 9g to 9b , from 9b to 9. Since the BANKS and 5 c - 5y elements are open, the AND 1 1 ,, - 11 закры- elements and the AND 4b elements are closed, only the AND 4 t element opens. As a result, the following is obtained at the device outputs the sequence of binary codes: 4, 3, 2, 5, 1, 6.

In the device, each subsequent permutation is obtained from the previous one by cyclically shifting the information to the right in two cycles simultaneously. The entire set of information registers is randomly divided into two groups. In the group of memory registers from k-ro to the nth register, a cyclic shift of information occurs and at the same time in a group of memory registers from 1st to 1 (the kO register also occurs a cyclic shift of information. At that, the number k is chosen randomly and the likelihood changes in the contents of all registers are equalized. Therefore, the device improves the quality of random search of permutations by equalizing the probabilities of changing the contents of all bits of the device and at the same time reducing correlations.

Lore Mula Invention

A device for randomly searching permutations containing a clock pulse generator, a decoder, a random code generator, a first group of AND blocks, a first group of BANNER blocks, two groups of OR blocks, a group of memory registers, the clock pulse output connected to the clock input of the generator a random code, the output of which is the connecting group and with the ith output of the decoder, characterized in that, in order to improve the accuracy of equalization of probabilities and decorrelation of permutations, The second group of blocks of elements AND is introduced, the second group of blocks of BANKS and the OR element, the outputs of the decipher-} driver are connected to the corresponding inputs of the OR element, the output of which is connected to the first input of the first block of AND elements of the first group and the synchronizing inputs of the group registers,

not with the input of the decoder, the output of the first input of the decoder is connected to the input unit AND the first group input of the 1st unit

connected to the information input of the first- BANNER of the second group and the first input

The 1st block of AND elements of the second group, the second input of which is connected to the output of the 1st register of the group and the output to the first input of the 1st block of the OR elements of the second group, the second input of which is connected to. exit 1st

group memory register, output of the i-th (i 1, .., p-1), where n is the number of permutations) of the group memory register is connected to the direct input of the i-ro block of the BANNER elements of the first group and is the output The 1st device permutation element, the output of the nth memory register is the output of the nth device permutation element, the output of the (1 + 1) -th block of elements AND of the first group is connected to the first input of the 1st block of OR elements of the first group, the output of the 1st block of elements OR of the first group is connected to the information input (iM) -ro of the group memory register, the second input 1st block of elements OR of the first group

connected to the output of the i-ro block of the element 35 GROUP, the code of the first block of the BANNER elements of the first group, the inverse input of which is connected to the first input (i + O-ro of the block of elements AND perto OR the second group is connected to the second input of the first block of elements And the first group .

6441376

group and with the i-th output of the decoder, characterized in that, in order to improve the accuracy of equalization of probabilities and decorrelation of permutations, the second group of blocks of elements AND, the second group of blocks of elements BANNER and the element OR, and the outputs of the descriptors } The driver is connected to the corresponding inputs of the OR element, the output of which is connected to the first input of the first block of AND elements of the first group and the synchronizing inputs of the group registers,

block of the BANNER elements of the second group, the direct input of the j-th (j 1, ..., n-2) block of the BAN elements of the second group is connected to the second input (jH) -ro of the block of elements AND of the second group and with the output (j +1) -ro of the block of ISH1 elements of the second group, the direct input (n - - 1) of the block of elements of the PROHIBITION of the second group is connected to the second input of the n-th block of elements AND of the second group and with the output of the n-th memory register

Comrade OR of the second group is connected to the second input of the first block of elements AND of the first group.

Claims (1)

Claim A device for randomly sorting permutations, containing a clock generator, a decoder, a random code generator, a first group of AND blocks of elements, a first group of blocks of FORBID elements, two groups of blocks of OR elements, a group of 10 memory registers, and the output of a clock generator is connected to the clock input of the random code generator, the output of which is connected to the decoder input, the output of the first 15 block of elements And the first group is connected to the information input of the first register of the group memory, the output of the i-th (i = 1, .., n-1), where η is the number of permutation elements) of the group memory register & is connected to the direct input of the i-ro block of the FORBID elements of the first group and is the output of the i-ro device permutation element, the output of the memory register is the output of the ^ 5 ηth device permutation element, the output of the (i + 1) -th block of elements AND of the first group is connected to the first input of the i-ro block of elements OR of the first group, the output of the i-ro block of elements 30 items OR of the first group is connected to the information input (i + l) -ro of the register group memory, the second input of the i-ro block of elements OR of the first group is connected to the output of the i-ro block of elements is 35 BANS of the first group, whose inverse input is connected to the first input of the (i + 1) -th block of elements AND of the first group and with the i-th output of the decoder, characterized in that, in order to increase accuracy equalization of probabilities and decorrelation of permutations, it additionally introduces a second group of blocks of AND elements, a second group of blocks of FORBID elements and an OR element, and the outputs of the decoder are connected to the corresponding inputs of the OR element, the output of which is connected to the first input of the first block of AND elements of the first PP and synchronizing inputs of the registers of the group, the i-th input of the decoder is connected to the inverse input of the i-th block of elements FORBID of the second group and the first input of the i-ro block of elements AND of the second group, the second input of which is connected to the output of the i-ro register of the group memory, and output - with the first input of the i-ro block of elements OR of the second group, the second input of which is connected and the output of the i-ro block of elements is FORBID of the second group, the direct input of the j-th (j = 1, ..., η-2) block of elements is FORBID the second group is connected to the second input (j + 1) -ro of the block of elements AND of the second group and to the output (j + 1) -ro lock of the OR elements of the second group, the direct input of the (n - 1) -th block of the elements FORBID of the second group is connected to the second input of the η-th block of elements AND of the second group and with the output of the η-th memory register of the group, the output of the first block of elements OR of the second group is connected with the second input of the first block of elements AND of the first group.