RU1783512C - Device for sorting numbers - Google Patents

Description

1

(21) 4822863/24 (22) 07.05.90

(46) 12/23/92. Bull. No. 47 (72) S.N. Makaren, V.I. Benkevich, M.M. Tatur and V.M. Buloichik

(56) Copyright certificate of the USSR No. 1300459, cl. G 06 F7 / 08, 1985

USSR copyright certificate Mg 1441384, class G 06 F 7 / 06.1986 (prototype). (54) NUMBER SORTING DEVICE

(57) The invention relates to computing, in particular to apparatuses for supporting the computing process, and can be used in specialized computing devices for apparatusing the function of sorting numbers. The aim of the invention is to simplify the device. The device contains ring shift registers 1, shift registers of the result 2, p triggers 3. counter 4, groups of elements AND 5, 6, 7, 12, element OR 8. element AND 9. delay elements 10, 11. The device performs ordering of numbers Ascending . 2 ill.

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The device relates to computing, in particular to devices for hardware support of the computing process, and can be used in specialized computing devices for 5 hardware implementations of the function of sorting numbers.

A device for sorting numbers (1) is known, containing two groups of n counters (n is the number of sortable numbers), 10 a group of n prohibition elements, the first and second input elements AND, an OR element, a shift register, and an analysis unit containing n triggers, a group of n elements OR, a group of (n-1) elements AND, elements 15 AND, NOT.

The closest to the expected technical result and the achieved result is a device for sorting numbers (2), selected as a prototype.

The device contains p t-bit circular shift registers, an AND-OR control element, n 2-OR elements, two AND elements, one OR element, a laziness control unit, three trigger groups, (n-2) AND elements. (p-1) elements OR.

The disadvantage of this device is its great complexity.

The aim of the invention is to simplify the device.

The device includes t m-bit circular shift registers, where n is the number of sortable numbers, n flip-flops, the first group of AND elements, OR element, 35 AND element, and the information inputs of the 1st m-bit circular register shift are the inputs of the corresponding sortable numbers of the device, and the high-order output is connected to the first input of the 1st element

cop And the first group, the second

whose input is connected to the output of the 1st trigger, and the output is connected to the i-th input of the OR element. The device additionally contains a counter, the second, third and fourth groups of AND elements, the first and second delay elements, n result shift registers, the output of the OR element being connected to the least significant bit input of the first result shift register and with the first input 5 (. the house of the And element, the output of which is connected to the direct inputs of the And elements of the second group, the outputs of which are connected to the zero inputs of the corresponding triggers, the device sync input is connected to the second input of the And element and through the first delay element with the sync input E m-bit circular shift registers, the result of shift registers and summing inputs counter output overflow koto55

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It is connected to the first inputs of the AND elements of the third group and through the second delay element with the inputs of the unit into the single state of the triggers. The output of the 1st trigger is connected to the inverse input of the 1st AND element of the fourth group and the second input of the AND element of the third group, the output of which is connected to the zeroing input of the 1st m-bit ring shift register. The direct input of the first element AND of the fourth group is connected to the third input of the element AND of the third group and the input of the logical unit of the device, the output j-ro of the element M

the fourth group 0 1n-1) is connected to

the direct input of the 0 + 1) -th element AND of the fourth group and with the third input of the element AND of the third group. The output of the high-order bit j-ro of the result shift register is connected to the input of the low-order bit Q + 1) -ro of the result shift register, the outputs of the result shift registers are the outputs of the sortable numbers of the device.

In FIG. 1 is a structural diagram of a device; in FIG. 2 is a work diagram.

A device for sorting p-bit numbers contains a group of input ring shift registers 1. a group of shift registers of result 3, a group of triggers 3, a counter 4, a first 5, a second 6, a third 7 of a group of AND elements, an OR element 8, an AND element 9, the first 10, the second 11 delay elements, the fourth group of elements And 12.

The device has a group of inputs 13, a synchro input 14, a group of outputs the 15.1st input of device 13 (1 1, p) is connected to the information inputs of the {register 1, the output of the highest category of which is connected to the first input of the 1st element And 5 whose output is connected to the ith input of the OR element. 8 and with the inverse input of the 1st element And 6, the output of which is connected to the zero input of the 1st trigger 3, the output of which is connected to the second input of the 1st element And 5, the inverse input of the 1st element And 7 and the first input 1- the first element And 12, the output of which is connected to the input of zeroing of the 1st register 1. The synchro input of the device 14 is connected to the second, the input of the element And 9 and the input of the delay element 10, the output of which is connected to the sync inputs of the registers 1, 2 and with the summing input of the counter 4 the overflow output of which is connected to the third inputs of the And 12 elements and to the input delay element 11, the output of which is connected to the unit inputs. triggers 3. The output J-ro of the element And 7 O T, n-1) is connected to the direct input Q + 1) -ro of the element And 7 and to the second input (j +1) -ro

of the And 12 element, the potential of a logical unit is applied to the direct input of the first And 7 element and to the second input of the first And 12 element. The output of the OR element 8 is connected to the input of the least significant bit of the first register 2 and with the first input of the And 9 element. The output of which is connected to the direct inputs of the And 6 elements. The output of the highest bit j-ro of Register 2 is connected to the input of the least significant bit 0+ 1 ) of register 2. The outputs of bits j-ro of register 2 are connected to the 1st output of device 15.

The principle of operation of the device is as follows. Initial numbers are written in registers 1 by parallel code, a sequence of mn pulses is sent to sync input 14, With the arrival of the first m pulses (t is the bit capacity of the numbers), the maximum of n numbers is extracted and written in sequential code to the first register 2. The allocated maximum number is excluded from for further consideration (the corresponding register 1 is reset), With the arrival of the next m pulses, the maximum of the remaining (n-1) numbers is allocated, which is written in the first register 2, and its contents are rewritten after code in the second register 2, etc. Isolation of the maximum of n numbers consists in a sequential analysis of the contents of the same-rank bits (starting with the highest) of the compared numbers.

The device operates as follows. In the initial state, the initial numbers are recorded in the registers 1 at the inputs 13, the counter 4 is reset, the triggers 3 are in the single state, the AND 5 elements are open, the high-order bits of the analyzed numbers go to the inputs of the OR 8. input 14 of the device receives a sequence of mn pulses (Fig. 2, plot 1). With the arrival of the first pulse, the state of triggers 3 changes according to the following rule: if the high-order bits of all numbers are zero, the output of OR 8 is zero, and 9 closed, trigger state 3 unchanged a. If the leading bits of all numbers are equal to one, the output of OR elements 8 is one, the And element 9 is open, and all And 6 elements are closed, the state of triggers 3 does not change.

If the high-order bits of some numbers are equal to one, and the high-order bits of the remaining numbers are equal to zero, then at the output of the OR element, the unit, the And 9 element is open and the And 6 elements are open. The inverse input of which receives a logic zero signal. The pulse from input 14 through the element And 9 and

open elements AND 6 nullifies the corresponding triggers 3.

When the 1st trigger 3 goes to zero

state corresponding element AND

5 5 closes and the corresponding number of

register 1 is excluded from the following

consideration.

After the delay time gy determined by element 10, the clock arrives at the clock inputs of registers 1, 2 (Fig. 2, diagram 2). In this case, the information in the t, 2 registers is shifted one bit to the right. In the low order of the first register 2, information is recorded from

5 of the output of the OR element 8. In the circular shift register 1, the value of the high order is overwritten in the low order. The pulse from the output of the delay element 10, in addition, increases the state of the counter

0 4 per unit. Similarly, the device works when the following pulses

With the arrival of the hth pulse count, the analysis of the last (younger)

5 bits of the initial numbers and after the delay time the information in the registers is shifted. Thus, after the arrival of the first synchronization pulses (moment T0 in Fig. 2, ep. 2) in the first

In register 2 is the allocated maximum number, in registers 1 are the original numbers in their original representation.

With the arrival of m pulses at the input of counter 5, an impulse appears at its overflow output, and the counter is reset. The pulse from the output of the overflow counter 4 (see Fig. 2, ep. 3) is fed to the input of the elements And 12 and to the input of the delay element 11

0 The group of elements And 12 and the input of the delay element 11, The group of elements And 7, And 12 are a priority scheme and is intended to reset the register 1 containing the selected maximum

5 is a number, which is indicated by the single state of the corresponding trigger 3. If in registers 1 there are two or more identical maximum numbers, then several corresponding triggers 3 are in

Q is a single state. With the arrival of an overflow pulse from the output of the counter 4 to the inputs of the elements And 12. At the output of one of the elements And 12, a zeroing pulse is generated and, if there are two or more identical maximum numbers, the corresponding register 1 with the minimum sequence number is reset. Thus, the allocated maximum number is excluded from further analysis.

After the delay time Hz, determined by element 11 (see, Fig. 2, ep. 4), the overflow pulse sets the triggers 3 to a single state and with the arrival of the (m + 1) th synchronization pulse, the separation of the maximum remaining (n -1) numbers

At the end of work, registers 2 contain an ordered sequence of numbers, the first register 2 being the smallest of the numbers, and in the nth register 2 the maximum of the numbers. Registers 1 are reset.

Thus, the proposed device sorts t-bit numbers and has less complexity than the known device.

Claims (1)

SUMMARY OF THE INVENTION A device for sorting numbers containing n m-bit annular shift registers, where n is the number of sortable numbers, n triggers, the first group of AND elements, the OR element. the AND element, the information inputs of the 1st t-bit ring shift register being the inputs of the corresponding sortable numbers of the device, and the high-order output is connected to the first input of the 1st And element of the first group, the second input of which is connected to the output 1st trigger, and the output is connected to the 1st input of the OR element, characterized in that, for the sake of simplicity, it contains a counter, a second, third and fourth group of elements I. the first and second delay elements, n shift registers tata, and the output of the OR element is connected to the low-order input of the first shift register of the result and to the first input of the And element, the output of which is connected to the direct inputs of the And elements of the second group, the outputs of which are connected to the installation inputs in О of the corresponding triggers, the device sync input is connected to the second input of the And element and through the first delay element with the clock inputs of the t-bit ring shift registers, the result shift registers and with the summing counter input, the overflow output of which is connected to the first inputs of the elements of the third group and through the second delay element with the inputs of the installation in the single state of the triggers, the i-ro trigger output is connected to the inverse input of the 1st element of the fourth group and the second input of the element of the third group, the output of which is connected to the zero input 1- th t-bit circular shift register, the direct input of the first element And the fourth group is connected to the third input of the element And the third group and the input of the logical unit of the device, the output j-ro of the element And the fourth group p-1) is connected to the direct input (j +1) -ro eleme And of the fourth group and with the third input of the AND element of the third group, the output of the high order j-ro of the result shift register is connected to the input of the low order of the () +1) -th result shift register, the outputs of the result shift registers are the outputs of the device’s sortable numbers .