RU1797118C - Multichannel signature analyzer - Google Patents

Abstract

The invention relates to computer technology and can be used in test diagnostic systems for discrete objects. The purpose of the invention is to increase speed. The multichannel signature analyzer contains two counters, two comparison units, an indication unit, two indicators, a group of AND elements, three forwarders, three storage units for reference signatures, two triggers, an OR element, three And elements, a delay element and a one-shot. The analyzer provides control of binary sequences simultaneously on several channels and gives information about the presence in the analyzed sequence of vectors of one erroneous vector or erroneous vectors of greater multiplicity. If there is one error vector, the analyzer automatically indicates its location. 1 ill.

Description

The invention relates to digital computing and can be used in test diagnostic systems for digital devices.

The aim of the invention is to increase the speed of the analyzer by making it possible to extract from the signatures additional diagnostic information about the error rate in multichannel binary sequences.

The drawing shows a diagram of the analyzer.

The analyzer contains signature generators 1, 2. 3, memory blocks 4, 5, 6 reference signatures, comparison blocks 7, 8, counters 9, 10, triggers 11,12, display unit 13, one-shot 14, indicator .15, OR element 16, indicator 17, elements 18, 19, 20 AND, group of elements AND 21, delay element 22, group of inputs of the initial installation 23,

clock input 24, a group of information inputs 25-7-25 - K, input 26 reset and input Start 27.

Let N be the number of K-bit vectors of the sequence under investigation that are fed to the information inputs 25-1 of the analyzer (K is the bit depth of the signature formers).

Counter 9 and trigger 11 form a (K + 1) -digit summing counter, counter 10 is a (K + 1) -digit subtracting counter.

Signature conditioners, counters, triggers are triggered along the leading edge of the pulse signals arriving at them.

The single-shot 14 along the leading edge of the signal generates a single pulse with the duration necessary to set the trigger 11 in a single state, and less

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the duration of the period of clock pulses supplied to the input 24 of the analyzer .;

Reference signatures should be calculated for a number of measures equal to 2 - -1, regardless of N.

Shapers 1, 3 are K-bit parallel signature registers, i.e. multi-input shift registers with linear feedback defined by forming primitive and distinct polynomials from one another. . . . ..

Shaper 2 is K independent of each other counting triggers, the counting inputs of which are information inputs of the second signature shaper 2. Thus, the shaper 2 performs bitwise summation modulo the two studied information vectors.

The element And 20 and the single-shot 14 serve to set the trigger 11 into a single state, which can be considered: zero bit of the counter 9, only at the moment when the high-order bit of the counter 9 is set to unity, and The final bits of this counter go to the zero state, and only if there were erroneous bits (bits) in the information vectors being studied ..

To satisfy the latter requirement is used. delay element 22, the delay time of which must be longer than the response time of trigger 11 and less than the duration of the period of clock pulses supplied to the input 24 of the analyzer. , ..: .....:. -:

Element And 18 stops the supply of clock pulses in the event that there are no erroneous bits in the studied information vectors or if they occurred, but compensated each other in both formators 1 and 2 of the signatures (the probability of this case is very small) and the highest order of counter 9 set to one and the remaining bits to zero; erroneous bits occurred in the investigated information vectors, the high order of counter 9 is set to one, and the contents of signature generators 1, 2 are not zero and coincided, i.e. at the output of block 7, the logic zero is forwarded; erroneous bits occurred in the information vectors under study, but in one of the signature generators they cancel each other out, and in the other they do not, and the high-order bit of counter 9 is set to the zero state.

In the event that only one erroneous vector occurred in the studied information vectors, then at the end of the work

the analyzer in the shaper 1, 3 will have the same content at the output of the block

8, a logic zero level will be set. Otherwise, the output of block 8 will be

logical unit level. Let the output of block 8 correspond to the least significant bit of the displayed binary number. Then, the indication of a binary code consisting of all zeros and ones in the high order at the end of the analyzer operation means that erroneous bits in the information vectors under study are absent or compensated in all three signature formers (the probability of this is very small); indication

5 code, consisting of all zeros (low-order state is arbitrary) means that erroneous bits in the information vectors under study occur, but in the first 1 or second 2 signal generators, the erroneous bits cancel each other out; an indication of a code in the low order of which is one means that the multiplicity of erroneous vectors is more than one, and finally, an indication of a code in the low order of 5 which has zero, and in the rest, a combination of zeros and ones, means that in the information vectors under investigation there was one erroneous vector, and the displayed code (with the exception of the high and low bits) represents the measure number on which the erroneous vector appears.

The analyzer works as follows ....

5, by the external signal supplied to the reset input 26, all bits of the signature drivers 1, 2, 3 are set to zero. By an external signal supplied to the input of Start 27, counter 9

0 is set to zero, triggers 11, 12 are set to zero, the reference signatures from the outputs of the first 4, second 5 and third 6 block of reference signatures are entered respectively in 5 formers 1, 2, .3 of signatures and from the inputs 24-0 -24-K the initial setting is entered the binary code of the number N in the counter 10., At the same time, the inverse output of the high-order bit of the counter 10 appears logical

0 unit (since N 2k-1), which allows the passage of signals through the element And 19 and through the group of elements And 21. In addition, the output of the high-order bit of the counter

9, a logic zero is set, therefore, at the output of the OR element 16, a logical unit is enabled, allowing the synchronization pulses to pass through the And 18 element, and since the trigger 12 is set to zero, a logic unit is set at its inverse output, which also allows the passage of clock pulses through the element And 18. Logical zero at the output of the high-order bit of the counter

9 locks the And element 20,

The clock pulses from the input 24 of the analyzer through the element And 18 arrive. To the counting input of the trigger 11, which is the zero bit of the counter 9, through the elements 18, 19 And the clock goes to the subtracting input of the counter 10, through the element And 18 and the element 22 delays, clock pulses arrive at the clock inputs of the first 1, second 2, and third 3 signature drivers.

The vectors under study from the information inputs 5-1-g 25-K of the analyzer through a group of elements And 21 go to the information inputs of the formers 1-3 signatures. The analyzer compresses the sequence of vectors under study. After N analyzer clock cycles, the signatures of the error vector will be generated in the shapers 1.3, and the error vector in the shaper 2. In all bits of the counter

10 will be zeros, and at the inverse output of the high-order bit of counter 10 there will be a logic unit that still allows the clock to pass through the And 18 element and the information to pass through the And group of elements And the 21 (M + 1) -th clock pulse sets to counter high-order inverse output 1.0. Logic zero, which prohibits the arrival of clock pulses through the And 19 element and the passage of the studied information through the And 21 element group, The clock pulses arriving at the clock inputs of the signature drivers are delayed by the Element 22 is the delay, however, when an input of the signature 1 pridet- (N + lj-th synchronizing signal, transfer the test vectors through a group of AND gates 21 will be already prohibited. This counter 10 completes its operation.

.:. ; . Suppose there were no erroneous bits in the vectors under study. Then, after N analyzer clock cycles, the contents of the formers 1-3 will be zero, and at the output of block 7 a logical zero will appear, which locks the And element 20. The counter formed by the counter 9 and trigger 11 counts up to 2k, the output of the highest order of this counter is set logical unit, at the output of the OR element 16, a logical zero is generated, which prohibits the passage of clock pulses through the And element 18. At the output of block 8, there will be a logical zero. This completes the work of the analyzer with the indication of a binary number, in the high order of which is one, and in the rest - zeros.

Suppose, in the investigated information vectors there were erroneous bits (moreover, all erroneous bits were in one erroneous information vector). Then, after N analyzer clock cycles, the contents of the first 1, second 2, and third 3 signature generators will not be zero, and the output of block 7 will be a logical unit. When the counter formed by counter 9 and trigger 1 T counts to 2x, a logical unit is set at the output of the high-order bit of this counter, a logical unit is displayed at the output of element I.20, a leading edge is seen at the input of one-shot 14, and a leading edge is displayed at its output a single pulse will occur which will set the trigger 11 to a single state. Subsequently, the signature changes in the first 1 and third 3 signature generators and the clock counts in the counter formed by the counter 9 and trigger 11, until the contents of the signature generators 1, 2 match, and the output of block 7 is logical zero, at the output of the OR element 16, a logical zero also occurs, which prohibits the passage of clock pulses through the And element 18. At the output of block 8, there will be a logical zero - a sign that there is only one error vector. This completes the operation of the analyzer with the indication of the binary code of the serial number of the measure, on which the erroneous vector of information is detected.

In the case when there are several erroneous information vectors in the vectors under study, the analyzer operates similarly to the considered case when such a vector is one, except that upon completion of the analyzer operation a binary number will be displayed, in the low order of which is one (a sign of the multiplicity of erroneous vectors).

Claims (1)

The claims A multichannel signature analyzer containing two counters, an indication unit, a first indicator, an OR element, first and second AND elements, first and second signature generators, first and second reference signal storage units, the reset inputs of the first and second signature generators are combined to form a reset input analyzer, read inputs of the first and second reference signature storage units, the installation input of the first counter and the parallel load input of the second counter are combined to form the start of the analyzer, group of information inputs of the second counter forms a group of inputs of the initial setup of the analyzer, the group of the bit outputs of the first counter is connected to the group of inputs of the display unit, the output of the first element And is connected to the clock input of the second counter, the inverse output of the Last bit of which is connected to the first input of the first element And, the group of information the outputs of the first and second reference signature storage units are connected respectively to input groups of the initial installation of the first and second signature generators, characterized in that, in order to increase the In terms of performance, it additionally contains a third AND element, first and second counting triggers, a single vibrator, a delay element, a group of AND elements, a second indicator, a third signature generator, a third reference signature storage unit, the output of the first comparison unit being connected to the first input of the OR element and the first the input of the second element And, the second input of which is connected to the direct output of the last bit of the first counter in. the last output version of which is connected to the second input of the OR element and to the clock input of the first trigger, whose inverse output is connected to the first output of the third element I. The second input of which is connected to the output of the OR element, the output of the third AND element is connected to the clock input of the second trigger, the second input of the first AND element and the input of the delay element, the output of which is connected to the clock and inputs of the signature drivers, groups of information inputs which are bitwise combined and connected to the outputs of the corresponding elements AND groups whose first inputs are combined and are connected to the inverse output of the last bit of the second counter, the output of the second d while comparison and the direct output of the second trigger are connected respectively to the inputs of the first and second indicators, the inverse output of the second trigger is connected to the clock input of the first counter, the output of the second element And is connected to the input of one Novibrator, the output of which is connected to the installation input of the second trigger, the input the reset of which is combined with the reset input of the first and trigger and the read input of the third reference signature storage unit and is connected to the analyzer start input, the reset input of the third signature generator is connected to the analyzer reset input, the third input of the third element And forms the analyzer clock input, the group of information outputs of the third block storage of reference signatures connected to the group of inputs of the initial installation of the third signature driver, the group of information outputs of the first driver is connected to the first groups of inputs of the first and second blocks comparison, the groups of information outputs of the second and third signature generators are connected to the second groups of inputs of the first and second comparison blocks, respectively, the second inputs of the elements groups form a group of information inputs of the analyzer.