SU924703A1 - Square rooting device - Google Patents

Description

The invention relates to computing and to be used for the hardware implementation of the square root operation in universal and specialized computers.

A device for extracting a square root is known, comprising a pulse generator, elements AND, a counter, an accumulator of the accumulator type. The extraction of the square root in it is carried out by counting the sum of members of a number of consecutive odd numbers 1.

The main disadvantage of a known device is its low speed, determined by the number of calculation cycles, depending on the range of numbers.

The closest in technical essence to the present invention is a device for calculating a square root containing input and output registers, a control unit, a squaring unit, a comparison circuit, a digit selection unit 2,

The residual of the known device is its low speed, firstly caused by the formation of only one digit of the result in each step, secondly, the need to square the number in each step, the bit size of which is equal to the bit depth.

The calculation time of the square root in a known device is approximately equal to

T,

 where n is the size of the root expression;

ten

 - time squaring of n-digit numbers.

The aim of the invention is to increase the speed of the device.

The goal is achieved

15 in that the device for calculating the square root, containing the input and output registers, the block for selecting the result numbers, bg control, introduced the shaper of the multiplier,

20 multiplication unit, subtractor and encoder, and the result digit selection block contains the address register, upper and lower registers f the memory block and the switch, and the input

Claims (2)

25 of the memory unit is connected to the output of the address register, the outputs of the memory unit are connected to the first inputs of the upper and lower register registers, the outputs of which are connected to the corresponding inputs of the switch, the output of which is connected to the inputs of the address register, the output register and the first inputs of the factor multiplier and the multiplication unit, the second inputs of which are connected respectively to the output of the output register shift and the output of the multiplier generator, the first and second inputs of the encoder are connected to the outputs of the higher bits corresponding to input and output registers, and the output of the sub-encoder to the second input of the lower register, the output of the multiplication unit is connected to the input of the subtracted subtractor, the input of which is decremented is connected to the output of the input register and the output to the input input of the input register and the first input of the control unit, the second and the third inputs of which are connected to the outputs of the lower bits of the lower and upper values registers / outputs of the control unit, from the first to the seventh, are connected to the control inputs of the input and output of registers, multipliers shaper, address registers, the lower and upper values of the switch, respectively.  The control unit contains two memory arrays, a delay line, a micro-command address decoder register, a clock signal generator, a condition decoder, OR NOT elements, a CLAIM: NEAR OR, a trigger, a shift register, and the clock generator output is connected to the first address of the address decoder microinstructions, the output of which is connected to the first inputs of the first and second memory matrices and to the first input of the condition decoder, the second and third inputs of which are connected to the outputs of the OR-NOT elements and EXCLUSIVE OR, respectively, output decryption This condition is connected to the second input of the second memory matrix, the output of which is connected via a delay line to the input of the register, the output of which is connected to the address decoder of the microinstructions, the inputs of the OR-NOT element are the first input of the control unit, the inputs of the EXCLUSIVE OR are respectively the second and the third input of the control unit, the fourth input of the condition decoder is connected to the low-order output of the shift register, the output of the second one is connected to the second and third outputs of the control unit, first, second, fourth, five The first and second outputs of the first matrix of memory are the first, second, fourth, fifth and sixth outputs of the control unit, the seventh output of which is connected to the trigger output, the inverse input krtorrr connected to the first input of the element OR NOT, the shift register inputs and the trigger is connected to the third and seventh outputs of the first memory matrix, respectively.  FIG.  1 shows a block diagram of a device for calculating a square root; in fig.  2 - the functional diagram of the memory block and encoder; in fig.  3 is a diagram of the implementation of the selection of four-digit result; in fig.  4 is a functional diagram of a factor multiplier; in fig. 5 is a functional block multiplication circuit; in fig.  6 is a functional block diagram of the control unit; in fig.  1 is a flowchart of the algorithm of the proposed device.  A device for calculating the square root (FIG.  1) contains input 1 and output 2 registers, control block 3, memory block 4, address register 5, lower 6 registers and upper 7 values, switch 8, blocks 4-8 are combined into the result digits block, encoder 9, driver 10 multiplier, multiplier I, multiplier 12, outputs 13 and 14 of the higher bits of registers 1 and 2, respectively, output and shift input 15 and 16 of registers 2 and 1, respectively, outputs 17 and 18 of the lower bits of registers b and 1, respectively, outputs 19 25 control unit 3.  Memory block 4 and encoder 9 (FIG. 2) contain memory elements including an address decoder 26 and a memory array 27.  The shaper factor 10 (FIG.  4) contains groups of elements AND 28 and a group of elements OR 29.  The multiplication unit 11 (FIG.  5) contains adders 30, the first and second inputs of which are 31 and 32, the control input 33, and the low-order output. 34  Control unit 3 (FIG.  b) contains the first 35 and second 36 memory matrix, delay line 37, register 38, decoder 39 addresses of micro-instructions, 40 clock signal generator, condition decoder 41, OR-NOT 42 element, EXCLUSIVE OR 43 element, trigger 44 switch 44 shift register.  GSA (FIG.  7) contains vertices 46-54.  At the GSA, the information at the outputs of the combinational nodes is indicated by the letter A with the corresponding position assigned to the combinational node.  In the proposed device for calculating the square root of the input 1 and output 2 registers, the register 5 addresses and registers b and 7 can be implemented on D-triggers.  It is assumed that memory block 4, KOMMVtator 8, encoder 9, shaper 10, multiplier 11 and subtractor 12 are implemented in the form of combinational circuits. In this case, the synthesis of memory block 4 and encoder 9-can be produced by known methods.  truth tables.  The memory block 4 and the encoder 9 can also be implemented on the memory elements having an address decoder.  This reduces the amount of equipment and ensures the regularity of their structures.  Memory element (FIG.  2) contains the address decoder 26 and the matrix 27. memory elements, the output of address decoder 26 being connected to the input of memory array 27, the output of which is the input of the memory element whose input is the input of address decoder 26.  Switch 8 contains in each category two AND elements, the outputs of which are connected to the inputs of the OR element.   .  The memory block 4, the address register 5, the registers of the lower 6 and the upper 7 values, and the switch 8 are designed to select the K result numbers (K takes integer values within 3 K, n the width of the root expression) Registers 5 - 7 have K bit Dov, and memory block 4 contains 2K (2 - 1) storage elements.  The diagram shown in FIG.  3 illustrates the sequence in which the four-digit result is selected.  At the top of the diagram is the value (for K 4 it is equal to 8).  The values of the two subsequent quantities formed from the previous one differ from it by t 2, where i is the level number of the location of the subsequent quantities (1 i K).  The top of the diagram corresponds to the first level.  The value of the previous value is placed in the address register 5, which determines the address of the address and by which from the memory block 4 in the lower value register 6 the subsequent value is read less than the lower value and the next value greater than the previous value in the upper value register 7.  The desired value is selected by control unit 3 via switch 8 from register b or register 7.  Using the encoder 9, an initial approximate value is formed (xi successive K digits of the result based on the contents of the upper bits of the input register 1 (d) and output register 2 (x).  For this purpose, tables of values of xgplg and xd are constructed for all possible combinations of the values of d and x.  According to the chart for the selection of K figures for the result of FIG.  3) an approximate value of x is determined so that by specifying it all the values in the range from x to x d can be obtained.  For example, let K 4, X mA Y, x c 14, Then, to obtain all values in the range from 10 to 14, it is necessary according to the diagram in FIG.  3 is the approximate value of x 12. Vechychiny X „,,. &Apos; and X d are determined, a descent from the subquired representation.  D expression in the form of D, (p x.  ) is equivalent to M 1-1 D, S (2 SX, - + x,) x-, 1Г-1 de х- - the value of K of the result figures determined in the i-th cycle and taking into account their weight position - the number of cycles required to determine n digits of the result.  For definiteness, we assume that the value of the radicand is the normalized number: D 1.  After the end of the i-th.  the cycle is formed by the remainder d / D- (with X D) then equivalent to i ,, ,,,,.  I -Vtii il /.  ° -KtiM) iFvvX 1P (, 4) (.  Suppose that the first input of the encoder 9 is connected to (K + 1) high bits of input register 1, and the second input of the encoder 9 is connected to K high bits of output register 2.  In view of this, the inequality {) is transformed into an equivalent one; - 2 (x + 2-m) We show that for i 1 Xmin To do this, we write down 2 (X-2-) main part of the inequality in the form; l {va-4, which implies that ve. 1 is exactly x, - + 1 bit or less.  Therefore, we accept.   d 2 (x + 2-) From inequality (2) with 1 1 it follows that d × 2 tnO 1 2x,,.   V3, X For i 1 we have: x, Yd + 21 Taking into account the weight positions of x- and d-values and ensuring the value of x in the range of O x-2, which determines the factor 2, the formulas are connected to the output of switch 8, and the second input The group of elements AND 28 with the output 21 of the control unit 3 is the control input of the generator 10, and the output of each group of elements AND 28 is connected to the first input of the group of elements OR 29 according to their weight position, the second input of the group of elements 29 is shifted by the shift circuit 15 with the output of the output register 2 and the output of the group of elements OR 29 is the output shaper 10 With the help of the last one in the 1st cycle, the value (2Сх | + x) is formed, which is equal to twice the contents of register 2 (111х-) incoming to the second input of the group of elements OR 29, increased by the value (x-), coming from the switch output 8, taking into account the weight position t of the group of K numbers of the result, which are determined in this cycle, by issuing blocks 3 of the corresponding control signal to the second input of the desired group of elements 28.  The multiplication unit 11 can be implemented according to the matrix principle, as shown in FIG.  five.  It contains K (n + 1) bit combinational adders 30, shifted relative to each other by one bit, first.  The input input 31 of each of which is connected to the output of the imaging unit 10, and the second input, one 32 all adders, the edge of the first, to the output values of the first bits of the previous adder 30 (for the first adder 30, its input 32 is zero) the control input 33 of each, the adder 30 is connected to the corresponding bit supplied to the first input of the multiplication unit 11 from the output of the switch 8, the output of the last adder 30, as well as the outputs 34 of the lower order of all other adders 30 are the output of the multiplication unit 11, which is a modified way of multiplying with minor bits  If the value at the control input 33 of the adder 30 is one, a number arriving at its first input 31 is transferred to the input of the adder 30, if zero, then zeros are transmitted.  Using multiplication unit 11, the product is formed,.  .  The control unit 3 can be implemented according to the microprogram principle according to the Wilks scheme with the memory of micro-instructions in the form of two storage elements 27, as shown in FIG.  6  The first 35 and second 36 memory arrays are permanent storage devices (ROM), the selection of which is performed by driving the corresponding bus.  The first matrix 35 is an accumulator of specific sets of control signals.  The selection of the necessary set of control signals is carried out by exciting the corresponding bus of the matrix 35 with signals from the outputs of the decoder of the micro-instructions 39.  The signals formed at the outputs of the matrix 35, as signals of micro-operations, go to the necessary nodes of the device.  The control unit 3 forms four microcommands corresponding to vertices 47, 51, 52 and 53 GSA.  The second matrix 36 is designed to control the sequence of execution of micro-instructions.  The selection of the required address of the next micro-command is made by exciting the corresponding bus-matrix 36 with signals from the output of the decoder 39 when executing those micro-commands that are not checked for transition conditions, and signals from the output of the decoder 41 conditions when executing the micro-commands that have transitions .  Thus, after the execution of microcommands corresponding to vertices 52 and 53 of GSA, the conditions of transition are absent, and after the execution of microcommands corresponding to vertices 47 and 51 of GSA, verification of the conditions of transition is performed. The signals of the decoder 41 excite one of the three tires of the matrix 36, corresponding to the transition to the execution of one of the microcommands, the actions of which are indicated by the vertices 51 53 GSA.  These signals are formed in accordance with the following logical expressions:)) where B5, Bjij and B5E are signals at the output of the decoder 41 to form a transition to the vertices 51, 52 and 53 of the GSA, respectively; Y 48 transition conditions corresponding to vertices 48, 49 and 50 GSA, formed during the execution of the current microcommand.  The condition corresponding to the GSA vertex 48 and indicating that a zero subtraction result was detected is formed by the OR-NOT 42 element.  The condition corresponding to vertex 49 of the GSA and indicating that the values in the lower bits of registers 6 and 7 are different, is formed by the element EXCLUSIVE OR 43.  To control the output register 2, the driver 10, and the bit register 45 is used as the clock counter.  In each operation cycle of the device in the shift register 45, a one-by-one advancement of the logical unit is performed.  This allows you to control the corresponding group of elements And 28 of the generator 10 and record information in the required K bit to register 2 (the moment of recording in register 2 is determined by the signal from the corresponding output 20).  Since the value of the logical unit is in accordance with the lowest bit of the shift register 45 only in the latter. then the state of this bit will determine the last beat (vertex 50 gsa).   A clock signal generator is predetermined for setting a specific sampling rate of control signal sets at a constant clock duration.  The pulses from its output go to the decoder 39 and, depending on the address code of the micro-command in register 38, excite the necessary busses of the matrices 35 and 36.  Since the code in register 38 should change only after all the processes associated with the execution of the current microcommand have been completed, the codes from the output of the second matrix 36 are supplied to register 38 through the delay lines 37 included in each bit. chain.  To memorize the sign of the result of the subtraction, an iD-trigger 44 is used, the sign is written, the result of the subtraction and zeroing of the last is performed on the signals received at its control inputs from the corresponding outputs of the first matrix 35.  When controlling the register 6, signals from the corresponding outputs 23 are received at its control input. , matrices 35, which determine the reception of information into register 6 from the outputs of memory block 4 or encoder 9.  . When controlling the register 7, signals from the corresponding outputs 24 of the matrix 35 are sent to its control input, which determine the reception of information into the register 7 from the output of memory block 4 or the reset of the register 7.  When the control unit 3 is operated, the decoder 39 selects one of the busbars of the matrix 35 using the address code of the micro-command located with the register 38, the decoder 39.  When / the clock signals from the generator 40 are generated, all the necessary control signals are generated.  A sample of the address of the next microcommand from the matrix 36 is made by the decoder 39 if no conditional transition is performed after the microcommand that is executed.  If it is executed, then the signal from the decoder 39 allows the analysis of the conditions of the transition using the decoder.  41 conditions.  After the formation of conditions pere-.  the course and their analysis, the decoder 41 selects the address of the next microcommand from the matrix 36.  The selected address is written to register 38 through the Erem, determined by the magnitude of the delay lines 37.   The device for calculating the square root works as follows.  In the initial state, the input register 1 contains the radic expression, the output register 2, registers 5-7, the shift register 45 and the trigger 44 of the control unit 3 contain zeros, each digit of the device is determined by the digits of the result.  The following is done for this.  The contents of the micro-command address register 38 reads the first micro-command {top-end 47 GSA) which places in the lower value register b formed by the encoder 9 an approximate value of the next K result numbers, zeroes the register 7 and advances the unit in the shift register 45. (in the first unit, the unit is pushed into the high bit of the shift register 45). Since the contents of the flip-flop 44, which controls the switch 8, is zero, the output of the switch b (x), which is also recorded in jierHCTp 5 of the address, is output to the switch 8 output.  Same value (x. ), arriving at first, entering shaper 10, jointly;. with the contents of the output PeX) i, arriving at the vuhistra. Swarm the entrance of the former 10 through the chain 15. a shift by one bit towards the higher bits, is used to form a value of 1 fa X.  + x With the help of block 11 multiplication the value is formed. X; (5. r, x 4U;) X,), which in subtractor 12 is subtracted from the contents of input register 1.  Next, the transition conditions are checked.  If a non-zero subtraction result is obtained, then the second micro-instruction (vertex 51 GSA) will be executed until the contents of the low-order bits 17 and 18 of registers 6 and 7 will not differ between themselves or the zero subtraction result will be obtained.  The second microinstruction writes the sign of the result of the subtraction into TpjHrrep 44 and, based on the contents of register 5, addresses from block 4 of memory selects the values in registers b and 7.  Further, depending on the state of the trigger 44 controlling the switch 8, the contents of register 6 or 7 arrive at the switch output.  If the trigger 44 is recorded zero (minus sign), then the contents of register b are received, if units are written (plus sign), then the contents of register 7 are entered.  Thereafter, the value x from the output of the switch 8 is written to the address register 5 and is used to generate the value. l x,),), ana.  R is logically described above.  If, after the next verification of the transition conditions, a non-zero subtraction result is obtained, but the contents of the low-order bits 17 and 18 of registers 6 and 7 are different, which corresponds to the exact definition of the next K numbers of the result, and this is not the last step, then one third of the microinstruction (ver The GSA bus 52), in which the value coming from the output of the switch 8 is written to the corresponding K bits of the output-register 2, and the result of subtraction from the output of the subtractor 12 along the 16-K shift circuit to the bits towards the higher bits is written to the input p Trunk 1.  The trigger 44 is zeroed, after which an unconditional return to the execution of the first micro-instruction is performed.  If after the next verification of the transition conditions, a zero result is obtained, subtract. or in the last step: the contents of the low-order bits 17 and 18 of registers b and 7 are different, which corresponds to the exact definition of the K digits of the result, then the actions (vertex 53 GSA), similar to those performed in the third micro-command, are performed, but after this the square root calculation process .  Output register 2 contains the result of the square root calculation.  Thus, the proposed unit for calculating the square root makes it possible to generate a result for cycles, while it is known for steps, and the duration of a cycle is t gc5, c {1 n--), subtraction time (n + k) 8 consecutive numbers is the value that determines the average number of steps that must be performed in each step to determine the K digits of the result, taking into account the predicted value of K digits.  The value is determined by Cmvtotfl m-1 Ty G2.  where m is the number of steps that must be performed (2 m. K + 1); m is the number of: cases in which, in order to get K figures of the result, m steps are required.  Therefore, the speed of the device increases in t.  ,  - time.  W, The advantages of the proposed device for calculating the square root is that it reduces the calculation time of the square root by about 3.87 times, the calculation is made under the assumption that n 64, K 4, then E 2.75, and the subtractor and the multiplier block adders are implemented according to the scheme with through transfer propagation, the first input of the encoder is connected to (K + 1) high-order bits of the input register, the second input of the encoder is connected to K high-resolution bits of the output register.  Claim 1, A device for calculating the square root. The input and output registers, the result selection block, the control block, are different in that, in order to increase speed, a multiplier generator, multiplier unit, subtractor and encoder are entered into it, and the result selection block contains the address register, upper registers and the lower values, the memory unit and the switch, the memory unit input is connected to the output of the address register, the memory unit outputs are connected to the first inputs of the upper and lower value registers, the outputs of which are connected to the corresponding.  the switch inputs whose output is connected to the inputs of the address register, the output register and the first inputs of the multiplier and multiplication unit, the second Bkoes of which are connected respectively to the output register shift output and the output of the multiplier generator, and the first and second cryptographic inputs are connected to the higher outputs bits, respectively, of the input and output registers, and the encoder input code is connected to the second input of the lower value register, the output of the multiplication unit is connected to the input of the subtracted subtractor, the stroke of which is decremented is connected to the input register output, and the output to the input register shift input to the first input of the control unit, the second and third inputs of which are connected to the output bits of the lower and upper values registers / outputs of the control unit, from the first to the seventh, . connected to the control inputs of the input and output registers, the driver of the multiplier, address registers, lower and upper values, the switch, respectively. 2. The device according to claim 1, wherein the control unit contains two memory matrices a delay line, a register, a micro-instruction decoder, a clock signal generator, a condition decoder, OR NOT elements, an EXCLUSIVE OR, a trigger, a shift register, and the output clock generator is connected to the first input of the decoder of micro-instructions addresses, the output of which is connected to G by the first inputs of the first and second memory matrices and to the first input of the condition decoder, the second and third inputs of which are connected to the outputs of the elements OR NOT and EXCLUSIVE E OR, respectively, the output of the condition decoder is connected to the second input of the second memory matrix, the output of which is connected via a delay line to the input of the register, the output of which is connected to the input of the microinstruction address decoder, the inputs of the element are the first input of the control unit, the inputs of the EXCLUSIVE OR is The second and third inputs of the control unit, respectively; the fourth input of the condition decoder is connected to the low-order output of the shift register, the output of which is connected to the second and third outputs of the control unit The first, second, fourth, fifth and sixth outputs of the first memory matrix are respectively the first, second, fourth, fifth and sixth outputs of the control unit, the seventh output of which is connected to the trigger output, the inverse input of which is connected to the first input of the OR-NOT element, the inputs of the shift register and the trigger are connected to the third and seventh outputs of the first memory matrix, respectively Sources of information taken into account in the examination 1. USSR author's certificate number 394781, cl. G About F 7/38, 1971. 2. Authors certificate of the USSR 611208, cl. G 08 F 7/38, 1978 (prototype). 27 Fig.Z 2i -0 31 G. 31zg 35 thirty K1y thirty 3 Jz 33 19 20 21. 22 23 25 40 W 38 3S f four/ 42 J5 7743 feRe Reg. Start f (6 Expression not TrM-ziVVchitan. Reg. RK.7 "" / 74 .6ltr) y y (Ree.7lGr4) Rk.