SU935954A1 - Device for calculating differential equations - Google Patents

Description

I

The invention relates to computing and can be applied to solve systems of differential equations.

A device is known that solves differential equations, which are an integrating device and are intended for solving differential equations given in the form of Shannon 1.

The disadvantage of this solution is the impossibility of using sufficiently accurate self-initiating methods of numerical integration, which leads to low speed, especially in the initial part.

The closest technical solution to the invention is a device containing increment registers, the first residue register, whose outputs are colored to the inputs of the first adder connected to the inputs of the digit ejection unit, the second adder connected to the inputs of the second digit allocation unit,

In which the integration step is performed. During the time of addition and one multiplication.

However, this device does not have insufficient speed.

The aim of the invention is to increase speed.

The goal is achieved by the fact that the device containing the increment registers has two adders, two digit allocation units and the first residue register, the output of which is connected to the input of the remainder of the first adder, the output of the operand of which is connected to the input of the remainder of the first adder, the output of the operand of which is connected to the information the input of the first digit allocation unit, the output of the operand of the second adder is connected to the information input of the second digit-healing unit, entered into the residual register, the restraint (the switching unit and the switch, What are the outputs of the increment registers connected to the information inputs of the switches, the control inputs of which are connected to the output of the decision block, the information input of which is connected to the output of the first digit allocation unit, the output of the first and the output of the second switch are connected to the inputs of the increments of the first and second adders, respectively, the operands the adders are connected to the input of the device operand digit, the outputs of the first and second digit allocation unit are connected to the corresponding inputs of the first and second adders with responsibly, the outputs of the remainder of the adders are connected to the inputs of the corresponding registers, the control inputs of the digit extractor blocks, the residual registers and the decision block are connected to the clocking INPUT device, and the output of the second digit extraction block is connected to the output result of the device, and the digit allocator contains a register of constants adder and digit register, with the digit register output connected to the unit's output, the control input to the control input of the unit, S information input to the output of the adder, the first input to which connected to the output of constant register, and a second input connected to an information input unit in FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of a digit allocation unit. The device contains registers (Рр increments 1, switches (Кцд) 2.1 and 2.2, adders (С) of the remainder 3.1 and 3.2, registers (Рр) of the remainder 4.1 and 4.2, a block (Bf,) is exhausted 5.1 and 5.2, decisive block 6, INPUT (IN) 7 digits of the operand and VOUT 8 of the result and a clock input (IN) 9. Outputs of the headers of increments 1 are connected to the inputs of switches 2.1 and 2.2, whose outputs are offset by S and U bits, respectively to the left are connected to the inputs of sum maters 3.1 and 3.2, i.e., in the commumator 2.1, the output of the discharge, having a weight of 2, is connected in the adder 3 1 to the input of the discharge, nmecmcse, weight 2, and in the commutator A re 2.2 bit code with a weight of 2, pozvevlen to the input of the bit with a weight in the adder 3.2. The outputs of registers 4 and blocks 5 with a shift of one bit to the left are connected to the inputs of adders 3, the outputs of which are connected to the inputs of registers 4 and blocks 5. Input 7 with a shift to the y and U bits, respectively, to the right is connected to the inputs of adders 3.1 and 3.2, where --p-eogpCi-p -H), W-i4eogp (. 5 is the delay in occurrence expressed in Kosh: chesgve) at the output of block 6, the result figures with weight p relative to the arrival at the cr-o input of the argument number with the same weight, a / f | - The function of rounding laziness to the pancake of the largest larger integer. In addition, the outputs of block 5.1 are connected to the inputs of block 6, in which the right part associated with the control inputs of switches 2 is calculated, the output bus 8 is connected to the outputs of block 5.2, and the clock bus 9 is connected with the control inputs of registers 4 and blocks 5 and 6, the digits of the digit 5 contain the constant registers 10, the adder 11 and the register of the digit 12, the inputs of the block 5 and the outputs of the register 10 are connected to the inputs of the adder 11, the outputs of which are connected to the inputs of the register of the digit 12, the control input and which codes are control inputs and outputs block 5. As a decisive block, any arithmetic unit can be used that allows forming the result bits in sequence, as the post bits go to its inputs of the corresponding bits of the operands (i.e., the device allowing the simultaneous input of operands and the same result distribution). The device implements the implicit midpoint method.,. / Y (, 1) and works in an excess P -fichal numeral system, where digits take values from the set | R, .2, ..., Ra5, R2. the initial state (the initial state setting circuit is not bounceable) in the increment registers 1 the following codes are written: R () ti, ... R2, () ii | 2, ..., RifiK; In the registers of the constant 10, the codes are written, and in the registers 4 and 12, and zeros are written in the register. In each I-th calculation cycle, the input bus 7 enters the input bus 7, having a weight, where the number of digits is followed by the digits after which the key is fixed, and added to the corresponding digits of the adders 3 with the incoming codes from the outputs of the registers 4, blocks 5 and switches 2. Moreover, the digit coming from the output of block 6 controls switches 2 in such a way that the outputs of register I, containing the code f: ll / 2 a, are connected to the inputs of the adder 3.1 to the adder 3.2 - penicrp I, which is sociable. . At the same time, from the height of the block 5.2, the output bus 8 receives the value of the digit of the result that weighs. Each cycle is occupied by a signal in the clock bus 9, through which the cocks formed at the output of adders 3 are recorded in regasters 4, the codes formed at the output of adder 11, 5ggs to register 12, and block 6 is preparing to receive the next digit. The operation of the device using the example of integrating the differential level Y-Y for a binary number system with the numbers I, O, I, at H, 11010 fll, is illustrated by the attached table, where the result X Ilfcooof is obtained. The proposed device allows forming, at the output, bits of the value of the desired function at the M +1 th point with a U + 1 cycle hold relative to the input of the corresponding function bits at the point into the device. This allows for sequential connection of devices to proceed to the next integration step not after the end of the previous step, but immediately after the first digits of the result of this step. Thus, the integration steps in the And, And + 1, Gu1 + 2, .., using the proposed devices can be combined in time, and the execution time of the M steps is: T-KW + O - -OS where U1 is the resolution of the function; -fcti is the summation time, and the average execution time of one integration step with a fairly large number of steps M practically does not depend on the size of the functions and tends to (0 + 1). (For an example from this time, it is equal to four addition cycles.) In a known device, the integration process at this step cannot be ct interchanged with the integration process in the subsequent steps; and each integration step is performed in two additions and one multiplication, i.e. the integration time in a known device increases with an increase in the size and exceeds the average step time in the proposed device. If we take into account that in the known device (which implements the first-order integration ffmud), to obtain the same complexity as in the proposed (where the second-order formula is implemented), it is necessary to significantly reduce the integration step ( computation time) it is quite obvious that the purpose of the invention is achieved with the help of the proposed technical solution. The proposed device allows not only to reduce the computation time (due to the combination of operations related to one or different integration steps), but also to preserve the volume of computations as compared to realia $ 1 integrated methods. In the proposed device, at each integration step, only one value of the right part is calculated, whereas in the known device, when implementing the Runge-Kutt method, the right part must be calculated twice at each integration step.

1593595416

We get the result Vu4. SOUTH 1 input digits ogruzicov usgruitsgva, outputs

Claims (2)

1. Computational ycipoftcrBo for real, the outputs of the remainder of the adders of the Differential Equations, are contained to the inputs of the corresponding registrative increment registers, two adders, two fumes (the Allocation digits and the first remainder register, whose code is connected to the input of the triggered increments, two digits, two digits The output of the operand of which is connected to the information input of the first allocation unit 1GAF1, the output of the operand of the second adder is connected to the information input of the second allocation section of the digit, which is required to increase relations, the decision block is entered into it, two switches and the second register of the remainder of which is connected to the input of the remainder of the second adder, and the outputs of the increment registers are connected to the information inputs of the switches, the control inputs of which are connected to the output of the decision block, to the information input of which connected to the output of the first block allocation digits, the output of the first and vbssod second switch are connected to the inputs of the first and second adders respectively, the inputs of the operands of the adders are connected to The first and the second digit allocation units are connected to the coaxial inputs of the first and second adders, the control inputs of the digit detection unit, the residual registers and the soldering unit, and the output of the second digit allocation unit are connected to the output result of the device. 2. A device according to claim I, characterized in that the digit allocation unit comprises a constant register, an adder and a digit register, the digit register output connected to the output of the block, the control input to the control input of the block, -.a information input - to the output of the adder, the first input of which is connected to the output of the register of constants, and the second input is connected to the information input of the block, Sources of information, taken into account when testing the test 1. USSR certificate N 637833, cl. G 06 Jl / 02, 1975 2. Authors certificate USSR / 568060, Cl. G About J 1/02, 1974 (prototype.