SU662937A1 - Device for computing the function:y equals e raised to the x power - Google Patents

Description

  1, The proposed invention relates to the field of digital computing and can be used in digital computers and, -. devices built on rsnoye. large integrated circuits. i A device for calculating a function is known, which contains two totalizers, registers and counters 1. The residual of this device is oTHioc "extremely low speed. The closest to the invention in its technical essence is a device containing input and output registers, first and second adders, a shift register, a shift unit and an encoder, the input of which is connected to the output of the shift register, the output of the suitable register is connected to the first input of the first adder, the output of which is connected to the first input of the input register, the first and second inputs of the second adder are connected to the outputs of the shift block and the output register, respectively, and the output is connected to the first input of the output register 2 Failure com known device is the impossibility of execution. calculations, when not all the bits of the input word have been entered into the device, for example, when input information arrives, are sequentially discharged after discharge from digital measuring devices of bit balancing or analog-code converters. This reduces: Stroke system. Another disadvantage of the known device is the complexity of its integral design, which is associated with a large number of external leads, Préil aga yo yo from St Royst, and is very strong because it contains the first koiuBvtyTaTop, the first and second inputs which is connected to the outputs of the encoder and the shift register, respectively, and the output is connected. with the second input of the first adder, the first and second elements I, the first h. the second prohibition elements, the delay element, the trigger and the second switch, the inputs of which are connected to the outputs of the register shift a and the output register respectively, the first output of the second switch is connected to the first input of the first element AND and the prohibiting input of the first prohibition element, the first input of which is connected to the trigger output, the first input of which is connected to the second output of the second switch, and the second input - second

662937 ..

the inputs of the first elements of the prohibition and through the element of the shield - with the entrance of the cross-shift. Third entrance first

switch is connected to the first input

The second element I, the output of which is connected to the second input of the output register, and the second input - to the second input of the input register and the output of the second prohibition element, which prohibits the input of which is connected to the output of the first register, the inputs of the shift block are connected to the outputs of the shift register and output register respectively.

The drawing shows a flowchart of a device for calculating a function .15

The device includes an input register 1, the first adder 2, the shift register 3, the encoder 4 and the first switch 5. The outputs of the input register 1 are connected to the first inputs 20 of the first adder 2, the second inputs of which are connected to the outputs of the switch 5. The outputs of the adder 2 interconnections with inputs {eughister i, shift register 3 contains (n + 3) 25 bits. The outputs of the first and its bits are connected to the inputs of the encoder 4 and the switch 5. The outputs of the encoder 4 are connected to the second inputs of the switch 5.30

The device also includes an output register b, a second adder 7, a shift unit 8 and a second switch 9. The outputs of the output register b are connected to the first inputs of the second souwler 7, to the information inputs of the shift unit 8 and to the inputs of the second switch 9. Register outputs the shift 8 is connected to the bit inputs of the adder 7, the output of which is connected to the inputs of the external register 6. The outputs of the shift register 40, 3, are connected to the control input J of the shift unit 8 and the switch type 9. Each 1th digit of the shift register 3 is connected to shift input on i p Adds a shift block of 8, which is designed to shift the code from one to one Dyo. Therefore, the first n bits of the shift register 3 are connected to its controlling input.

The device also includes prohibition elements 10,11, elements And 12,13, trigger 14 and delay 1.5. The output of the delay element 15 is associated with the shift circuit of the shift register 3. The sign bit of the adder 2 is connected to the inverse of the barring element 10, the output of which is connected to the receive circuit of the input register code 1 and to the first input of the And 12 element. 12 is connected to the reception circuit of code 60 of the output register b. The first output of the switch 9 is connected to the input of the element I 13 and to the inverse input of the prohibition element 11. The second output of the switch 9 is connected to the information one 65

the input of the trigger 14, the output of which is associated with the input of the prohibition element 13,

The device also contains information inputs 16,17, control inputs 18-20 and outputs 21,22. The information inputs 16, 17 are connected to the control inputs of the switch 5. The control input 18 is connected to the input of the prohibition element 10. The control input 19 is connected to the third control input of the switch 5 and to the second input of the element 12.

The control input 20 is connected to the control input of the trigger 14 and the inputs of the prohibition element 11 and the element 13, the outputs of which are connected to the outputs 21.22. In addition, the control input 20 is connected to the input element of the charge 15.

Adders 2.7 can be combinational. Input and output registers can be constructed on the basis of triggers with an internal delay. Input register 1 contains n bits and output register 6 contains (n + 2) bits, with two-bit bits intended for storing the whole Part of the result.

- In the coder 4, the constants in (1 + 2) are written in the additional code, where i.l, 2 .... n.

Switch 5 contains n groups of elements And, three elements in each group. The first input of the first element And the 1st group is connected to the output (1-1) -th bit of the shift register 3.

The first input of the second element AND of each i-th group is connected with the output of the 1st i-ro digit of the shift register 3. The first g) 4th of the third element / AND of each 1st group is connected to the i-th output of the encoder. The second inputs of the AND elements of all three groups are associated respectively with the information inputs 16,17 and the control input 19. The outputs of the AND elements of each group are combined with the help of the OR elements.

Switch 9 is built from (n + 2) groups of elements I. Each group

consists of two elements I. The first input of the first element AND of each i-th group is associated with the output of the i-ro bit

output register 6. The first input of the second element AND of each i-th group is associated with the output (i + l) -ro of the output register b (it is assumed that the output bits of the output register 6 should be smaller numbers). The second inputs of elements AND of each i-th group are associated with the output (i + l) -ro of the shift register number 3. The outputs of the first elements AND of all groups are combined using the element OR, the output of which is “bdkey to the input of the element 13”. The outputs of the second elements AND of all groups are combined using the OR element, the output of which is connected to the input of the trigger 14. The proposed device operates as follows. In the initial state, in the first discharge of shift register 3, one is written, in the remaining bits - zero. In the output register 6, numbers equal to one are written, i.e. in the second category, the unit is recorded. Input register 1 is set to zero. The calculation of the function € is carried out in, (n + 3) cycles, each of which consists of six cycles. By the beginning of the first cycle of each i-ro cycle, information inputs 16,17 receive signals, the values of which characterize the value of the first bit of the operand (the operand enters, starting from the higher bits). If a single signal arrives at information input 16, then the next bit of the operand is numerically equal to 2. If a single signal arrives at information input 17, then the next bit of the operand is numerically equal to 1. If the single bit of time arrives from the information inputs 16.17, the next bit of the operand is numerically equal to 0. The value of the operand is limited. In the first clock cycle, the control signal received at the control input 18 is used to receive in register 1 a code from the output of adder 2. This code is numerically equal to the sum of the code recorded in register 1 to the beginning of the first clock cycle, and the code recorded in shift register 3 In this case, if a single signal arrives at information input 16, a one is added to the (1-1) th digit of the contents of input register 1. If a single signal arrives at information input 18, the unit is added to the i-th bit of the contents of input register 1. If information inputs 16.17 contain zeros, the contents of register 1 do not change. By the beginning of the second clock cycle, the signals from the information, inputs 16.17 lines, are on, and the control input 19 is set to a single signal, which is present until the end of the i-ro Computing cycle. In. the second, third, fourth, and fifth cycles of the control signal also goes to the control input 18. With this signal, register 1 produces: from receiving a code whose value is equal to the algebraic sum of the code that was in state 1 in register of the start of the clock and constants (1 + 2), which is selected from the encoder 4 by a single signal from the output of the i-ro bit of the shift register. If the value of this code turns out to be negative (which is indicated by the unit in the sign bit of adder 2), prohibition element 10 prohibits the passage of signals to receive the code in register 1. As a result, at the end of the fifth clock cycle in register 1 of the input word, a minimum positive balance is formed from subtracting from the contents, reg. 1 from the reference to four constants -Vp (1 + 2). The signals from the output of the prohibition element 10 through the element 12 allow the reception of the code from the outputs of the second sullator 7 to the output register 6. In the output register 6, the code is received, the value of which is equal to the sum of the code that was recorded in the output register 6 to the beginning of the beat, and the same code, shifted to the right on i bits. In the sixth cycle, the control signal received at control input 20 produces information at outputs 21.22. At the same time on; one input of the element And 13 and the inverse input of the element of the prohibition 11 receives the value (i-l) -ro of the output register 6 (information output is performed, starting from the 2nd cycle). In trigger 14, by this time the value of the same bit of the result was recorded, which was recorded in output register 6 by the beginning of the i-ro cycle. . If a single signal is present at output 21, this indicates that the next bit of the desired value of the function is numerically 2. If the single signal is output at 22, the next bit of the desired value of the function h is equal to 1. If however, the single signal does not appear at any of the outputs 21,22, which indicates that the next bit of the required value of the function is numerically equal to 0. After the control signal sent to the control El, the idle input 20, the contents of the i-bit yes output register 6 records the flip-flop 14. Kpofte addition, manufactured shift data in the shift register 3, to the right by one bit. In this computation one cycle terminates. as a result of the execution of (n + 3) tsik at outputs 21, 22, the discharge for discharge is generated sequentially. The value of the function Y, ref: 5 is put down by the redundant binary code of 0.1.2 in each bit. Consider the operation of the device by example. Let it be necessary to calculate the function at the point X 0,022102. The width of the operand and result representation. In tab. Figure 1 shows the values of conC ant,. (L + 2-), where, 2,3,4,5,6, the beginnings of which are expressed in an additional code. The calculation of the required value of 66293 5 10 7 .8 TpyHKUHH is illustrated in Table 2.3 during each calculation cycle. Table 2 shows the states of shift register 3, input register 1, the addition of two numbers on adder 2 in the first six cycles of calculations, since the operand is fed to the inputs of the device only in the first six cycles. The process of converting the argument in each cycle is shown until the remainder of the algebraic addition of the contents of register 1 and the constants becomes negative and the reception in register 1 is not performed. 6lit2

0,000000

Claim

about, 000100

0,0101002

0.001101 "

100,000,000

-0,000100

- 0.010100

.oioioo

1,111001

-0,001101

-0,001101

1,111001

-0.001010

, 001010

.11110Р

- 0.000110 - .. 0.000110

1.111100

"0.000010

d;

1,111110

000010000

-0.000000

0,000000662937

eleven

10; OOOTSG1-10, 000101

-51-10,000101 00.001000

10, 001101-1 o, 001101

- 10.001101 000100

, 010001 +00.000010

8 b

000000001 10,010101

10,010101 as a result of performing 9 cycles: in the calculations at the outputs of the device, the code 01.210101 / GO, ° 010101/2 2.328 was formed discharge by bit.

The value of the argument, 022102, / 0.110110 / 2, 845To.

The tabular value is € 0.845 2.32798.

From the considered example, it is triumphant that the value of the function in the proposed device is calculated in (n + 3) cycles, and, due to the time consuming processes of the one-time input of the operand and the calculation of the next digits of the result, the higher bits require the 6 values of the function that carry more information about him, calculated in the first cycles. This makes it possible to effectively use the proposed device S process control systems in real time, when the operand's digit generation process is limited by external factors, and the control effect for the executive body of the control system is formed directly from the results of the calculations. Determine the time.

12

oh oh

.

about

eleven

one

Required for the formation and testing of this control action In the proposed device, the most significant bit of the required function value is calculated in the second cycle and the control system executive begins to work out the obtained control action. For definiteness, we assume that the processing time of the controlling action by the executive body of the control system is tn (n + 3) t, where t is the period of arrival of the operand numbers, Then the time of formation and testing of the controlling action Tj is 2t4-tu.

Suppose that with. Then for the known device 2 we get T 60t + ty 100t, and T 2t + 40t 42t. Thus, in this case, the proposed device will reduce the time of formation and testing by the executive body of the control system by 2.5 times. In addition, the proposed device will increase the speed when working in a computing environment. Let K devices be connected in series, the computation time in each of which