SU1048472A1 - Device for dividing binary numbers - Google Patents

Abstract

1. A device for dividing BINARY NUMBERS, containing a register PW of the dividend, a divider and a private adder, an analysis unit and a control unit, the outputs of the bits of the register of the private are connected to the outputs of the device, the inputs-devices, are connected to the information inputs of the bits of the register divider, the outputs the bits of the registers of the dividend and the divider are connected to informational: the inputs of the bits of the adder, the outputs of the adder are connected to the information inputs of the register of the dividend, the outputs of the direct and inverse values of the higher bits of the register The limit is connected to the inputs of the analysis unit, the outputs of which are connected to the inputs of the control unit, the first output of which is connected to the control inputs of the shift of the dividend and master registers, the second and third outputs of the control unit are connected to the control inputs of the issuance of the corresponding additional and direct divider register codes, the fourth the output of the control unit is connected to the input of the control for receiving information from the register of the dividend, that is, and for the sake of simplification from the third, the fifth output of the control unit is setting n to the input sign bit divisor register, the output MSB of the dividend register is connected to the input of the least significant bit of the private register. 2. A device according to claim 1, characterized in that the control unit comprises a pulse generator, a counter, AND, OR elements, a zero decoder, pulse distributors and a switch, the output of the pulse generator connected to the input O) of the first pulse distributor, the first output of which connected to n -. the second output of the first element OR, the output of which is connected to the information input of the switch, the control input of which is connected to the first input of the block, and the first exit of the second distributor of pulses, the first output of which is connected to the first inputs of p. The second elements And, the second inputs of which are connected to the second and third inputs of the block, respectively, and the outputs are the second and third outputs of the block, respectively, the second output of the second pulse distributor is connected to the fourth output of the block, and the third output - with the first input of the second element OR | the second input of which is connected to the second output of the switch, and the output to the input of the third pulse distributor, the first output of which is connected to

Description

the input of the counter and with the first output of the block, and the second output with the control input of the decoder zero, information1048A72

the input inputs of which are connected to the outputs of the counter bits, and the output to the second input of the first element OR,

The invention relates to computing techniques, in particular to electrically-based digital computers.

Dividers are known that perform the operation of dividing binary numbers without restoring the remainder l.

However, in such devices, one binary step of summation (subtraction) is required to determine each binary private number, which adversely affects the time of the division operation.

Closest to the invention is a device for dividing binary numbers, containing divider and quotient registers, accumulating adder, comparison circuit, interrogator and control unit, whose outputs are connected to the first inputs of the divider registers, the private and accumulating adder, the first output of the divider register is connected with the second input of the accumulating adder, the first output of which is connected to the first input of the control unit, the third output of the accumulating adder is connected to the input of the polling unit, the output of which is under. chen to the second input of the control unit, the second divider and outputs a register accumulator connected to first and second inputs of the comparator circuit, the output of which is connected to the third input of the control unit. The known device provides an accelerated execution of the division operation due to the omission of the cycles of summation; (subtraction) for sufficiently small or sufficiently large in absolute value residuals. So, for example, if as a result of addition (subtraction) a positive residue is formed, containing in the leading bits of K zeros, then the closest (K-1) bits of the private zero. To obtain the following.

It is sufficient to shift the initial remainder by the K alevo bits and then subtract the divider from it. Similarly, a sufficiently small in absolute value negative residue is obtained, which contains K higher units. At the same time (K-1), the nearest bits of the private unit and the initial balance is sufficient for obtaining the next residue. move the remainder by K bits to the left and then add a divider to it. The cases of small in absolute magnitude residues reveal a polling unit that analyzes the code in the three highest bits of the accumulating adder containing the remainder. The cases of large residuals are revealed by comparing the circuit by comparing the four most significant bits of the divider code and the next, residual code. If the compared codes are close, then without a prior shift, one more step of addition (subtraction) is performed, as a result of which a small absolute value is formed, the remainder, for which the rules for the formation of the next particular bits are stated above. If the remainder is neither small enough, nor large enough, then the usual method is used to determine the bits of the bits, in which the values of the bits of the bits are determined in the control block by the sign of the remainder i.

Thus, in a known device, the discharges of a quotient are formed according to different rules for residues of various sizes, which makes the known device more complicated.

The purpose of the invention is to simplify the device.

To achieve this goal, in the device for dividing binary numbers, containing the registers of the dividend, divider and private, the adder, the analysis unit and the control unit, the outputs of the private register are connected to the outputs of the device, the inputs of the device are connected to the information inputs of the bits of the divider register, the outputs of the bits of the registers of the dividend and the divider are connected to the inputs of the bits of the adder; the outputs of the adder are connected to the information inputs of the register of the dividend, the outputs of the direct and inverse values of the higher bits. The register hub is connected to the inputs of the analysis unit, the outputs of which are connected to the inputs of the control unit, the first output of which is connected to the control inputs of the shift of the dividend and private, the second and third output of the control unit are connected to the output control inputs of the respective additional and direct divider register codes , the fourth output of the control unit is connected to the control input of receiving the dividend register, the fifth output of the control unit is connected to the input of setting the sign bit of the register el, the output of the higher bit of the register of the dividend is connected to the input of the lower bit of the private register, the control unit contains a pulse generator, a counter, elements AND, OR, a decoder zero, pulse distributors, and a switch, with the output of the pulse generator connected to the input of the first pulse distributor , the first output of which is connected to the fifth output of the unit, and the second output to the first input of the first OR element, the output of which is connected, to the information input of the switch, the control input of which is connected to the first input at the block, and the first exit - to the input of the second pulse distributor, the first output of which is connected to the first inputs of the first and second elements AND, the second inputs of which are connected to the second and t | e inputs of the block, respectively, as well. the outputs are the second and third outputs of the block, the second output of the second pulse distributor is connected to the fourth output of the block, and the third output is the first input of the second OR element, the second input of which is connected to the second output of the CMB switch, and the output is to the input of the third impulse distributor with the input of the counter and with the first output of the block, and the second output with the control input of the decoder zero, the information inputs of which are connected to the outputs of the bits of the counter / and the input to the second input of the first element OR, FIG. 1 shows a block diagram of an apparatus for dividing binary numbers; in fig. 2 is a functional block diagram of the control unit; in fig. 3 block analysis. The device contains the divider register 1, the register of the dividend 2, the private register 3, the adder}, the control unit 5, the analysis unit 6, the input device Tsa 7, the device output 8. The control unit 5 contains the pulse generator 9, the pulse distributors 10, 11 and 12, the elements OR 13, elements AND 15 and 16, counter 17, switch 18, decoder zero 19, outputs 20-2, inputs 25, 2b and 27. Analysis unit 6 contains elements AND 28, 29, OR 30. NOT 31. The device performs division / - bit normalized binary numbers presented in direct codes, quotient is also formed in direct code. The order and sign of the quotient are determined according to known rules. Registers 1, 2 and 3 each have one additional bit, while registers 2 and 3 contain a shift to the left, register 1 may be non-shift. The adder t is a (p-1) -disc combinator type adder and adds the codes from registers 1 and 2, the result is written to register 2. The analysis unit 6 generates signals, where bd is the state (0 or 1). the first from the left (sign) bit of register 2 of the dividend; B is the SO state or 1) the second left (most fractional) bit of the same register. The value of the signals XQ, X, X2 is supplied from the outputs of the analysis unit 6 to the inputs 25, 26 and 27 of the control unit 5, respectively. Generator 9 generates a trigger pulse at the start of execution.

five

division operations. Distributors 10

11 and 12 provide the temporal distribution of control signals in accordance with the duration of the actions performed on each of these signals. Counter 17 is designed to count the number of cycles in such a way that it is set

to zero on all cycles. The decoder zero 19 connects the signal from the second output of the distributor

12 to the input of the element OR 13, in the event that the state of the counter is 17. and is equal to zero, thus ensuring the repetition of division cycles until the determination of all the quotient figures. If the state of the counter 17 becomes equal to zero, then the decoder zero 19 does not pass the signal to the input of the element OR 13 and the execution of the division cycles stops. Switch 1o switches incoming

its input signal or the input of the distributor 1 1 in the absence of SI1-

Qala at the input 25 of block 5, or at the input of the element OR H in the presence of a signal at the input 25 of block 5. Thereby, the composition of actions in each cycle is changed depending on the presence of the xy signal. If, then the division cycle is only a joint shift of registers 2 and 3 to the left by the control signal from the output 20 of block 5; if, then the addition of the codes of registers 1 and 2 is additionally performed in the cycle,

Before the start of the division operation, the divisor and the dividend codes are located in registers 1 and 2, respectively. The sign bit of each of the registers 1 and 2 contains a zero code, and in the highest fractional bit, the unit code, since the divisor and the dividend are normalized numbers. Since,, before the first cycle, the outputs of block 6 are set to X (, x 1,,. At the beginning of the division operation, generator 9 produces a trigger pulse, which is fed to the input of the pulse distributor 10. From the first output of the distributor 10, a pulse arrives at the output of block 5 and then to the input of the installation of the sign bit of register 1 and sets this bit to one state.From the second output of the distributor 10, through the element OR 13, the pulse goes to the information

the input of the switch 18. Since the control input of the switch 18 is in this. time a zero signal arrives () then a pulse passes to the input of the distributor of the divider 11. From this moment the execution of the first cycle begins. From the first output of the distributor 11, the pulse arrives at the first inputs of the elements 15 and 16. Since,,

then the impulse passes through the element

15 AND, the outputs 21 of block 5 and further. To the control input for issuing an additional divider register code 1. The additional register code 1 supplied to the adder 4 is represented as its inverse code and a single signal arriving at the low-order transfer input of the adder 4. Adder 4 is the sum of

an incoming code with a code from register 2. After a predetermined period of time, a control signal appears to the second output of the distributor 11. This signal. through the output 23 of block 5

is fed to the input control input of the register 2 information. When this signal arrives, a sum code is received in register 2 received on the adder C. In this case

the contents of the fractional digits of the sum are of the remainder in pr; or additional code, and co. held by the sign bit (O or; 1) is equal to the value of the first digit

private.

Let the contents of register 2, lc fbq i,.,, And the contents of register 1,. .,, c (f. In the case under consideration,, and the two higher digits of D are equal to one and therefore their inverse values. The result of adding B to the additional code

VD of D is equal to

S B4 D 01bjb3b OOd d,, ...., and „4

 about -s

t- -OQ o / i o

If the dividend is greater than or equal to, then adding P carries over to the highest fractional bit and

 - 1 + 0 + 1 0,

and the transfer to the sign bit rank Ro 1 Henceforth the value of the sign bit amount of the sum is

So bo + do + Po 0 + 0 + 1 K If the dividend is less than the divisor, the topereny R, 0 and Si 1 + 0 + 0 1, $ 0 0 + 0 + 0 0. Thus, for each of these cases the value of SQ coincides with the value of the digit of the code, and the value of $ 1 determines the sign of the remainder; if, then the remainder is positive and is represented in the direct code; if, then the remainder is negative and is represented in the additional code. Next, from the third output of the distributor 11 through the OR element 1, a pulse arrives at the input of the distributor 12. From the first output of the distributor 12, a control signal is fed to the input of the counter 17 and the output 20 of the control unit 5. From the output 20, the control signal is fed to the inputs of the shift register 2 and 3. Upon receipt of this signal, a joint shift of the contained registers 2 and 3 to the left by one bit is produced. As a result of the shift, the resulting quotient from the sign bit of register-2 is rewritten to the least significant bit of register 3, to its essay unit, in the off-set bit of the register of 2 eapi b1, the highest fractional bit of the remainder appears, in its place is the bit following it, and so on. Simultaneously with the shift, a unit is added (or subtracted) to the contents of counter 17. Next, from the second output of the distributor 12, a pulse is applied to the decoder zero 19 and, if the contents of counter 17 is not zero, from the output of the decoder 19 through the element OR 13 to the information switch input. 18. This completes the first division cycle. As a result of its implementation in the higher bits of the register, the following 2 new combinations may arise:. J for a positive balance: „for a negative balance Combination b | 1 exactly corresponds to the original combination (at the beginning of the division, therefore, I AM are repeated.: 72 Q -, 1-O corresponds to the Combination of a negative residue close to the divisor in absolute value. Therefore, in this case, unlike the described one, addition of the contents of register 2 with the direct code of the contents of register 1. Since the signal x is still zero, the pulse from the first output of switch 18 is fed to the input of the distributor 11 and farther from the first output of the distributor 11 to the first inputs of the And 15, 1b elements . in this case, and Xp 1, therefore the pulse passes through AND 16 to the output 22 of block 5 and further to the control input. issuing the direct code of the register of the divider 1, as a result of which the direct code of the register 1 is fed to the input of the adder as well as in the considered case, the value of SQ is equal to the value of the next private digit, and the value of 5 determines the sign of the newly obtained residue. In this case, Ob2 b,. . . , (,..., djj SgS Sj ,,., Sj If the code of the left-shifted remainder in absolute value is greater than the divisor code, then $ 1 0 + 1 + 0 1,, 5 1 + 1 + 0 0, i.e. the next quotient of the quotient is zero and the new remainder is also negative. If the code of the left-shifted remainder is in absolute magnitude less than or equal to the divisor code, r o P. 1 and 5 0 + 1 + 1 0: 5 1 + 1 + 1 1 I.e., the next digit of the individual is equal to one and the new balance will be positive. After the addition, the previously described actions for the case,, Combinations,, and Bo 1, repeat, correspond to a small absolute value of In this case, the addition clock can be skipped and the next quotient is equal to the value b ,, In this case, a single signal is sent to the control input of switch 18, so the pulse received at its information input switches to the second output and the OR 14 element is fed to the input of the distributor 12. Next, the registers 2 and 3 are shifted together in a similar way, counting the number of cycles and checking the end of division. After each offset, one of four possible combinations of b, b values occurs and the actions described earlier are repeated. The operation ends when the contents of the counter, 17 becomes equal. Thus, each division cycle depends on the contents of the meter. the upper bits of register 2 consist either of two ticks: the algebraic addition and shift ticks, or only from one ticks. Regardless of the actions performed, each cycle in the sign bit register of register 2 is determined by one digit of the quotient, which is transmitted ti the least significant bit of register 3 in the process of the joint shift of these registers. The time required to perform the division depends on the ratio of the number of addition cycles and shear cycles, since the latter are performed several times faster than the addition cycles. To estimate the speed of the proposed device, it is necessary to determine the expectation m.j. the number of shear cycles after the add cycle. After each step of the addition, one shift cycle is necessarily followed. The subsequent actions of the device depend on the contents of the two high bits of register 2 of the dividend. If the contents of these bits do not coincide with each other, then the addition cycle is performed, otherwise the shift cycle is performed. Subsequently, the shift cycles are repeated until the contents of the two higher 7210 bits of register 2 become different. Thus, the total number of shift cycles performed after the addition cycle is equal to the number of identical digits (zeros or ones) contained in the higher fractional digits of the sum S obtained. By calculation, it is possible to establish that the mathematical expectation of the number of subsequent cycles of the shift after cycle the addition is equal to n − 1, JPj for sufficiently large, and so on. - This means that after each step of the addition, 8/3 shear cycles are performed on average, i.e. for every 8 private bits, there is an average of 3 addition cycles. Denoting by T.J the execution time of the addition cycle, and after T.g the execution time of the shift cycle, we obtain the average TQ calculation time D) of the particular bits of the EHG CA5K TsV Thus, the device reduces, on average, the number of the addition cycles to 37.5. A further increase in the speed of the Device, like the prototype, can be obtained by introducing additional shift chains of the dividend and quotient registers by two, three, etc. bit and a corresponding increase in the number of analyzed bits of the register of the dividend. Therefore, the speed of this device is at least not lower than that of the prototype. The positive effect is to simplify the device, since it does not require different chains of formation of particular numbers for residues of various sizes. 26A.Zf 22 L. 27 JA

Ft

Claims (2)

1. A device for dividing binary numbers, containing the registers of the dividend, divider and private adder, an analysis unit and a control unit, the outputs of the bits of the register of the private connected to the outputs of the device, the inputs of the device, connected to the information inputs of the bits of the register of the divider, the outputs of the bits of the registers of the dividend and the divider is connected to the information _: inputs of the bits of the adder, the outputs of the adder are connected to the information inputs of the register of the dividend, the outputs of the direct and inverse values of the senior. bits of the register of the dividend connected to the inputs of the analysis unit, the outputs of which are connected to the inputs of the control unit, the first output of which is connected to the control inputs of the shift of the dividend and private registers, the second and third outputs of the control unit are connected to the control inputs of respectively issuing additional and direct 'divider register codes, the fourth block output the control is connected to the input of the reception control of information of the register of the dividend, with the fact that, in order to simplify the device, the fifth output of the control unit is connected to the input Fitting divisor register sign bit, MSB of the dividend register output connected to the input of LSB private register. 2. The device according to π. 1, characterized in that the control unit comprises a pulse generator, a counter, AND, OR elements, a zero decoder, pulse distributors and a switch, the output of the pulse generator being connected to the input of the first pulse distributor, the first output of which is connected to the fifth, fifth output of the block, and the second output is the first input of the first OR element, the output of which is connected to the information input of the switch, the control input of which is connected to the first input of the unit, and the first output is the input of the second pulse distributor, the first output of which th is connected to first inputs of first and second AND gates, whose second inputs are connected to second and third! block inputs, respectively, and the outputs are the second and third outputs of the block, respectively, the second output of the second pulse distributor is connected to the fourth output of the block, and the third output is connected to the first input of the second OR element, the second input of which is connected to the second output of the switch, and the output is to the input of the third pulse distributor, the first output of which is connected to, SU, „. 10484721048472 the counter input and with the first output the input inputs of which are connected to the block, and the second output - with the control-outputs of the bits of the counter, and the output input of the zero decoder, information - to the second input of the first OR element.