SU481042A1 - Device for solving systems of linear algebraic equations - Google Patents

Description

The invention is excluded from the computational technique and can be applied when modeling complex systems, to solve systems of linear algebraic equations, to build optimizers.

Specialized computing devices are known for solving systems of linear algebraic equations that implement the method for solving the corresponding differential equations and consist of a set of digital integrators. To solve the system of n equations with (dg-j -) -) a member in each, it is necessary to have ("+ + 1) digital integrators.

The aim of the invention is to simplify the device and increase its reliability to solve systems of high-order linear algebraic equations.

This goal is achieved by the fact that the proposed device contains a probability impulse converter, a multiplying-summing matrix connected to its outputs and a random binary number generator connected to the output of the clock generator, the output of which is connected to the second inputs of the integrators and with one input of the pulse potential. the converter, the other inputs of which are connected to the output of the control unit through the corresponding valves, the third inputs of the integrators with the multiplicative-sum outputs matrix, the other inputs of which are connected respectively to the outputs of the integrators and to the output of the generator of random binary numbers.

Ma drawing shows a block diagram of the proposed device.

The proposed ycTpoiiCTBo contains a generator of 1 clock pulses, a multichannel generator of 2 random binary numbers connected to the output of a clock pulse generator, a probability-nm pulse converter of coefficients 3, consisting of and :; the binary code register of the coefficient a // and the bit equivalent circuits (not shown in the drawing) associated with the inputs to the above registers and block 2; multiplying matrix 4, connected to the outputs of the generator 2, random binary numbers and the probability-impulse converter 3, the probability integrators 5, 6 and 7, each of which consists of a reversible counter and bit comparison circuits (not shown in the drawing), the inputs of the counters are connected to the outputs of multiply-su.mmiruyu H-ieii. Matrix 4, the inputs of the circuit. Comparison - to the parallel outputs of the counters and generator 2, and their outputs - to the outputs of the multiply summatrix; control unit 8 connected to clock generator 1

1: Impulse. iia The drawing shows the connection of the control with the valves U-1 / Nrism and the issuance of ko, 1, and in the case of yerpoueina rotations together with CMB.

13 based on the device layout); the best iteration method, which, when specified in the initial sys tems of the system, is searched for by the roots of the search engines and iriolies.

Roota device iachinats with the secret of the kofferento) ai, “12 ... oiij through) entil o, iu n 1 / into registers of probable 11L) a} L 1; but; about the factor co-ordinator 3, i, eg-. This-in reverse counters are trusted for intitrators on, o, and / through gates 9, i 1, and 13. 11 after the generator has been started / accidentally in 4Hceji, the generation of coefficients ai, ai2, ... a ;, pi, 32 occurs. ..n i are statistical impulses that are iodine to the input of the resistive-modulating matrix. The multiplicity of probable IMIULUS REMOVALS is produced by “AND, addition-“ i-Lll-i. Iia outputs a multiply-summed matrix of 4 get random sequences of pulses, the likelihood of which is equal to the new values of the roots of the l-and that are estimated by probabilistic iptteratoram, b and 7. The system will come to di-aiamic balance when 5, 6, and 7 set the codes corresponding to those of this equation system. Through gates 10, 12 and 14, the root codes are described in a digital computational matrix of digital computers according to the digits of the control unit B.

Due to the fact that computational operations are performed with static streams of impulses, random failures do not affect the operation of the device. The decision time depends only on the required accuracy of determining the Kopneii p clock frequency.

Economy of equipment is achieved due to the simplicity of the probabilistic computational circuits constituting the multiplying-sum matrix 4.

B 1 known device on digital intratra tors main costs of equipping with a set of integrators for multiplying the matrix of coefficients

on the discharge of the approximate roots.

With n 30 n 10-bit adders, it is necessary to have about 27000 cases of microcircuits of the type “o () gnka-2” (from taking into account 3 cases per bit).

In the proposed device for realization, multiplying-summing, the matrips for it, the meii consists of 900 circuits "And for three inputs and 120 circuits" OR for eight inputs, it will take about 400 packages. The highest costs are equipped with 930 10-bit comparison circuits, for which approximately 14000 cases are required (from 1.5 cases pa 1) and 5p d). Thus, the equipment in the non-1-asm device is almost 2 times

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