SU798858A1 - Computing unit of digital network model for solving partial differential equations - Google Patents

Description

The invention relates to computing and can be used in the construction of devices for solving problems of mathematical physics, formulas / IXX partial differential equations. A computational node of the cyclic grid, containing a processor performing sequentially, bit by bit, arithmetic and logical operations and two memory blocks, is known. Its disadvantage is a large amount of equipment, since each computational node is a universal computing machine programmatically tuned. to perform the required sequence of actions, and low speed due to the sequential method of information processing. A digital grid computational node is known that contains a multi-input adder, a shift register, and 2 elements. The disadvantage of this node is the low accuracy of calculations due to the simple discarding of lower-order bits when performing division by a factor of four by shifting the register by two digits. For the considered node, the problem solving speed is low. This is a consequence of the fact that this node implements a simple iteration method for solving finite difference equations, which requires many iterations to obtain a solution. The closest in technical essence to the present invention is a computing node of a digital grid comprising a multi-input adder, a shift register, an element AND, a group of elements AND and a multiplier, the inputs of the adder are connected to the inputs of the node, the output of the adder is connected to the serial input of the multiplication unit, parallel inputs of the block the multiplications are connected to the group of code inputs of the node, the output of the multiplying block is connected to the serial input of the shift register, the serial output of the register is connected to the first input of the AND element, parallel Shift register outputs are connected to the first inputs 1 "1I elements AND group of elements, AND, IxBD of element I connected to the output of the node, outputs of elements AND group are connected; To parallel outputs of the node, the control inputs of the register and elements AND are connected to the control inputs of node 3 The disadvantage of the considered node is the low speed of solving problems. This is due to the fact that this node implements a simple iteration method for solving finite difference equations. The simple iteration method has slow convergence. Therefore, the solution of partial differential equations using the node in question requires a large number of iterations and, consequently, a large amount of time. The purpose of the invention is to increase the speed of interaction. The goal is achieved by the fact that the computational node containing the adder, multiplication unit, information inputs of which are connected respectively to information inputs, shift registers, AND elements, clock inputs of which are connected respectively to the clock inputs of the node, the output of the first And element is the output of the node , switches and a code converter are introduced into an additional code, the output of which is connected to the first input of the adder, the low-order bits of the first and second shift registers are connected respectively to ne the first inputs of the first and second switches, the second inputs of which and the input of the second element I are connected to the output of the adder, the output of the second element I is connected to the input of the multiplication unit, the output of the third switch is connected to the input of the code converter into the additional code, the information inputs of the fourth and fifth switches connected to the information inputs of the node, the output of the multiplication unit is connected to the input of the fifth switch, the outputs of the fourth and fifth switches are connected respectively to the second and to the third input The adders, the inputs of the third and sixth switches are connected to the low-order bits of the first and second shift registers, the output of the sixth switch is connected to the input of the first element And to the fourth input of the adder, the inputs of the seventh switch are connected to the outputs of the first and second shift registers, and the outputs of the seventh the switch are the information outputs of the node, the outputs of the first and second switches are connected respectively to the inputs of the higher bits of the first and second shift registers, the clock inputs of the switch The switches are connected to the clock inputs of the node. Figure 1 presents the block diagram of the proposed node; 2 shows the block diagram of the multiplication unit; Fig. 3 is a block diagram of a switch. The proposed node contains the adder 1, block 2 multiplication, registers 3 and 4 shift, converter 5 code to additional code, elements And b and 7, switches 8-14, information inputs 15-20 node, information outputs 21 and 22 node, clock inputs 23–40 nodes, trigger 41, a twister 42 codes, an adder 43 with memory transfer, in which the output of each bit is connected to the input of the next least significant bit, and the transfer output of the bit is connected to the bit input. The output of the low-order adder is connected to the output 45 of the multiplier. The information inputs 20 of the multiplication unit are connected to the inputs of the shaper code 42, the control inputs of which are connected to the output of the trigger 41 and the serial input 44 of the multiplication unit, which is also connected to the input of the trigger 41, the output of the lower digit of the adder is connected to the output 45 of the multiplication unit, each the author consists of elements AND 46 and 47 and the element OR 48, the inputs of the element OR 48 are connected to the outputs of the elements 46 and 47, the first inputs of which are connected to the inputs 49 and 50 of the switch, the output 51 of the switch is connected to the output of the element OR 48, the second ode elements and are connected with the control inputs of the switch 52 .and 53. The computational node allows calculating approximations to a solution in two neighboring nodes of the grid area using the algorithm U) /. Lk-1) .. (.. ,, ,, (, (. And). P., -V). Ch t 1P1 4 1 + di iH,:) - i V 1-2, J-ij. - iteration number; -number of column and row of the grid area; - the new solution of the problem in the grid nodes; - known quantities; - iteration parameter. The device works as follows. In the initial state in register 3 is, in register 4 - both values are represented by an additional code. The trigger 41 of the multiplication unit 2 is in the zero state. Next, the formula (1) is realized. During (n + 2) device operation cycles, single control signals are fed to the inputs 23, 29, 31, 37, 26, 39 and 40. This ensures that

from the next computational node in the row on input 17, receiving and and from neighboring nodes in the column on inputs 15 and 16, receiving f, -; input 19 from the block of the right parts of the grid model, receiving information from the output of adder 1 to the input of unit 2 multiply through element I b, output from register 4 through switch 14 to the input of adder 1 and to neighboring computing nodes through element I 7 through output 21, as well as the possibility of cyclic shift of registers 3 and 4 through switches 8 and 9, Converter 5 is designed to receive J additional code from the value supplied to it. This is necessary to perform the subtraction operation in formulas 1 and 2. During the first two clock cycles, register 3 does not shift. Since the switch 10 is closed at this time, as a result of this delay (i-tactically multiplied by a factor of four. Register 4 during these two clock cycles is shifted by the signal at input 36, and the serial code from the register output through switch 14 is blunt adder input, where it is summed up with the rest of the components coming from the output of converter 5, neighboring computational nodes of the grid model through switch 11 and the grid right side block through switch 12 through switch 9 lower register bits 4 during shift census They are replaced by the higher bits, i.e. the contents of register 4 are saved by cyclic shift. From the third: about the device operation cycle, a single signal is fed to the input 27, which ensures the transfer of the code from the output of the lower bit of the register 3 to the input of the converter 5 through the switch 10 and the shift signals are fed to the input 33. As a result, through the switch 8, the register 3 is cyclically shifted.

The next bit of the sum from the output of the adder 1 through the element And b is fed to the input 44 of block 2 multiplication. At the inputs 20 of the multiplication unit 2, a parallel code is applied to the value cw / 4, which is fed to the inputs of the code generator 42. The control inputs of the coder 42 of the codes receive the next bit of the sum from input 44 and the previous bit of the sum of the output of flip-flop 41. Depending on the values of this pair of bits, the coder of 42 codes issues a value to the inputs of the adder 4 and | | 4, an additional code from w / 4 or zero code. The output code (Shaper 42 is summed with the contents of adder 43. This thereby implements the well-known algorithm for multiplying numbers in additional codes. (Code Shaper 42 is a combinational circuit.

On the adder 43, the next partial product is formed, the least significant bit of which is fed to the output 45 of the multiplier 2.

On the n-th and (n + 1) -th cycles of operation J, the shift signal to register 4 is not applied. This is provided at (n + 1) ohms and (n + 2) th cycles required in the additional code for adding the sign bit to the higher bits, j-, and other corresponding variables in the neighboring computation nodes. At the (n + 2) th cycle of operation, the shift signal is applied to register 4.

As a result of this organization of work through (n + 2) cycles, the contents

5 registers 3 and 4 are restored.

Next, the trigger 41 of the multiplication unit is reset to zero and the operation of summing is performed during the n operation cycles of the device. For this, single signals are input.

dy 38, 24 and 32. The remaining control signals are zero. Shift signals are sent to register 3. As a result, the serial code from the output of the register 3 through the switch 14 is summed with the higher bits of the product, coming from the output 45 of the multiplier 2, through the switch 12 to the input of the adder. The result from the output of the adder through the switch 8

0 is written to register 3. Thus, after 2n + 2 operation cycles, register 3 stores the calculated new approximation.

- Further calculation of U ,,. (similar to the computation of IL. During the (n + 2) device operation cycles, single signals are fed to the inputs 23,30,31,37,26,39 and 40. This ensures that j is received from the neighboring computing node in the input line

0 18, reception .. and UiH.j.iH3 of the neighboring computing nodes in the column at inputs 15 and 16, reception at input 19 from the block of the right-hand parts of the grid mp3. During the first two clock cycles, register 4 is not shifted, which provides multiplication by a factor of four in formula (2). Register 3 is cyclically shifted at this time. From the third cycle of operation, a single

0 is fed to input 2B, as a result of which the code from the output of register 4 is fed to the input of the adder, and register 4 is cyclically shifted. The operation of the multiplication unit is similar to that described above. On the nth and (n + 1) th cycles of operation, the shift signal to register 3 is not applied. Thus, in (n + 2) clocks, the contents of registers 3 and 4 are restored. Further, after resetting the flip-flop 41, summation of the i, -i is

 . -hu f ii, 3 i, j, j .j-i iM.j i-nj /

For this, single signals are fed to inputs 39.25 and 32. Shift pulses are applied to register 4. After n steps in register 4, a new approximation will be learned.

Supply signals 34, 35 to the inputs of the switch 13 read the contents of registers 3 and 4 at outputs 22.

The problem solving time when using the invention is approximately N times less than when using a known node, where N is the number of nodes of the grid area in one direction.

Claims (3)

1. Evreinov E.V. and Kosarev Yu.G. Uniform high performance computing systems. Novosibirsk, Science, 1966, pp.38-41. 2. USSR author's certificate No. 546891, class C. 06 F. 15/34, 1975. 3. USSR Author's Certificate No. 608165, Cl. 06 F 15/32, 1975 (prototype). e kZ go 43 4f 2 TO 5J