SU763904A1 - Matrix microprocessor - Google Patents

Description

The invention relates to the field of computing and can be used in the construction of devices for solving the Dirichlet problem for multidimensional elliptic and parabolic equations of mathematical physics with the implementation of various computational patterns and grids. A device is known that contains a multi-input single-bit combinational adder of a sequential type with elements for memorizing transfers per one or a different number of ticks, a shift register, a register of functions, groups of input, output and control buses 1. The disadvantage of it is a large number of equipment, which It costs the construction of combinational adders and triggers to memorize the values of the result and the transfer for each combinational sum of the matrix. To construct a computational node for solving the three-dimensional Poisson equation, at least six three-input adders and 12 memory elements (triggers) are required to store the translations and results. The device has a range of applications, due to its orientation to the Laplace and Poisson equations, and is used to construct only two-dimensional digital grids. The closest technical solution to the proposed is a grid microprocessor consisting of a multiplexer, a counter with an intermediate register, a shift register of the result, and a switch of the result values or the value of the amount fixed in the current microcode in the low-order counter 2. The disadvantages of such a grid microprocessor include limited functionality, since it only solves problems with unit coefficients with higher derivatives, low speed, since the multiplication operation implemented by the device is performed in a time much longer than a single-type operation with one or several shift operations, as well as a complicated structure for performing the multiplication operation. In addition, the device cannot solve equations with variable coefficients,. The purpose of the invention is to enhance the functionality and speed of the device. This goal is achieved in that the device containing the multiplexing summing unit, the shift node, the first inputs of the multiplexer being the first group of inputs of the microprocessor, and the output of the multiplexer connected to the input of the summing unit, the output of which is connected to the first input of the shift node, the second input which is the first input of the microprocessor, and the output of the shift node is connected to its third input; according to the invention, an adder, a decision accumulation unit, an initial data storage unit, a residual storage unit, two elements are entered nta AND, increment trigger and coefficient storage unit. The first and second group of inputs of the coefficient storage unit are the second and third microprocessor groups, respectively. and the outputs of the coefficient storage unit are connected respectively to the second inputs of the multiplexer. The output of the shift node is connected to the first input of the adder, the output of which is connected to the first input of the initial data storage unit, the output of which is the first output of the device and connected to the second input of this unit and the first inputs of the decision accumulation unit, the storage unit of the remainder of the first element And the output which is connected to the input of the increment trigger, the output of which is the second output of the device, the output of the remainder storage unit is connected to its second input and connected to the first input of the second element AND whose output is connected to the second input of the adder, the output of the decision accumulation unit is the third output of the device, the second and third inputs of the decision accumulation unit are the second and third inputs of the microprocessor respectively, the third and fourth inputs of the source data storage unit are the fourth and fifth inputs of the microprocessor, the second the inputs of the first and second elements And are respectively the sixth and seventh inputs of the microprocessor, and the third input of the remainder storage unit is the eighth input of the microprocessor. The proposed device implements a new incremental method (or an incremental method), which avoids the classical multiplication method, traditional for such multiplication problems, reducing everything to an arithmetic operation of summing coefficients with one or several derived code shift operations with extracting and accumulating selected prirgii. The scheme of the proposed grid microprocessor shown in the drawing. It contains multiplexer 1, summation unit 2, shift node 3, coefficient storage unit 4, adder 5, source data storage unit b, first element and 7, decision accumulation unit 8, residual storage unit 9, second AND element 10, increment trigger 11. Grid microprocessor can be used as an internal node in solving problems of mathematical physics. The device works as follows. When preparing the device for operation, the coefficient storage unit 4, through the information inputs, numerically enters the values of the corresponding coefficients. The control signals of the coefficient storage unit 4 are connected to the triggers of the increments 11 of the respective adjacent grid microprocessors. Thus, if the next microprocessor adjacent to the microprocessor selected increment in the previous iteration (i.e., the oldest bit), then in the current iteration the output trigger signal of the increment trigger received on the control input of the coefficient storage unit will allow connection to the input of the multiplexer 1 (via one of the buses of the second group of information buses of the multiplexer) at the time of scanning the corresponding address of the multiplexer. If in the previous iteration, for example, increments were allocated in all neighboring microprocessors, then all four coefficients will be introduced through a multiplexer to the input of summing unit 2 in the current iteration. The coefficients can be added in successive, parallel, serial-parallel ways. As a result, using the summing block 2, the intermediate result will be obtained and stored in the shift node 3 sum of coefficients. For definiteness, we will assume in the following that operations are performed on numbers in a sequential code, the representation form is a fixed comma before the leading left significant digit after the sign one, and the processing of numbers in the summing block and adder starts from the youngest. Then the code of the obtained value sequentially, starting from the youngest, will be fed to the T first input of adder 5, to the second input of which through the second element 10, acting as a valve, the control signal will also receive the code of the remaining storage 9 . The result of the addition will be a number that serves as its new source data for the next

iteration, which will be recorded from the adder to the storage unit of the initial data on the corresponding control signal. Then, the resulting code is shifted already by the higher bits ahead. The initial shift begins with the most senior bit, and the subsequent ones begin with the bit in which the most significant bit different from the zero value was allocated in the previous iteration. The presence of the control signal at the second input of the first element AND the evidence of the 4th division of the corresponding increment in the entire device on this microtocess corresponding to, for example, the shift of the t-ro bit, fixes the state of the current bit of the original data of the grid microprocessor in question. The position number of the selected bit is fixed for the device as a whole and it determines the number (ti) of bits by which the code of the sum obtained in the next micro iteration in summing unit 2 and written to the shift node 3 is shifted to the lower bit. The presence of the higher order in this grid microprocessor is fixed by the trigger of increment 11. Further, since the output of the storage unit of the initial data is simultaneously wired to the information input of the decision accumulation unit, the selected increment weighing 2 must but to be summed up with the previously obtained increments in this block. The amount of increments received

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 y d. allocated in this micrK

a processor on each micro iteration, taken each time with its own weight, determined by the position number in the code sequence, and is an accumulated solution at a given grid node, or grid function, obtained each time by refining the previous value by the amount of the higher leading bit in the current iteration. The code in the source data storage unit 6 remaining after the allocation of the highest bit is a residual code. It is rewritten into the remainder storage unit 9, from which at the next iteration by shifting (but the youngest bits forward) will be connected to the input of the adder 5 through the first input of the first element I. Next, the residual code will be complicated with the summary result code obtained from ( +1) -th micro-iteration, which is equal to the sum of the coefficients corresponding to those grid microprocessors, in which on the C-th micro-iteration a high bit was allocated, shifted by bits to the side of the youngest, and so on.

Thus, this grid microprocessor provides a calculation of the nodal function, which ultimately consists of the sum of the increments (or higher bits allocated to each micro-iteracin from the original data. Hence the name of the method: the method of steps; values.

The technical and economic effect of the present invention as compared with the known one is in extending the functionality by solving equations with variable coefficients, increasing the device speed by replacing the multiplication operation with the addition operation of 5 coefficients and a one-time shift of the code thus obtained in a simple hardware implementation of the device.

20

the invention

Formula

A grid microprocessor containing a multiplexer, a summing unit, a shift node, with the first inputs

25 of the multiplexer is the first group of inputs of the microprocessor, and the output of the multiplexer is connected to the input of the summing unit, the output of which is connected to the first input of the offset node, the second input of which is the first input of the microprocessor, and the output of the offset node is connected to its third input, which is different that, in order to improve the speed and enhance the functional capabilities of the microprocessor by solving equations with variable coefficients, it was introduced into it 1 atop, a solution accumulation unit, a source data storage unit x, remainder storage unit, two AND gates, and flip-flop increment coefficient storage unit, the first and second group of inputs of which is respectively the second and third

5 by a group of inputs of the microprocessor, and the outputs of the coefficient storage unit are connected respectively to the second inputs of the multiplexer, the output of the shift unit is connected to the first input of the sum of the matrix, the output of which is connected to the first input of the storage unit of the initial data, the output of which is the first output of the device and connected to the second input this block and the first inputs of the accumulation unit of the solution, the storage unit of the remainder of the first element I, the output of which is connected to the input of the increment trigger, the output of which is the second output of the device and, output storing unit ostat0 ka connected to its second input and connected to a first input of the second AND gate, whose output is connected to the second input of the adder, the output of unit storage solution is

Claims (1)

Claim A grid microprocessor containing a multiplexer, a summing unit, a shift unit, while the first inputs of the multiplexer are the first group of microprocessor inputs, and the output of the multiplexer is connected to the input of the summing unit, the output of which is connected to the first input of the shift unit, the second input of which is the first input of the microprocessor, and the output of the shear assembly is connected to its third input, characterized in that, in order to improve performance and expand the functionality of the microprocessor by solving equations with ne with variable coefficients, an adder, a decision storage unit, a source data storage unit, a remainder storage unit, two And elements, an increment trigger and a coefficient storage unit are introduced into it, the first and second group of inputs of which are the second and third group of microprocessor inputs, respectively, and the outputs of the block coefficient storage are connected respectively to the second ·· inputs of the multiplexer, the output of the shear assembly is connected to the first input of the adder, the output of which is connected to the first input of the source data storage unit, the output which is the first output of the device and connected to the second input of this unit and the first inputs of the decision storage unit, the remainder storage unit of the first element AND, the output of which is connected to the input of the increment trigger, the output of which is the second output of the device, the output of the remainder storage unit is connected to its second input and connected to the first input of the second element And, the output of which is connected to the second input of the adder, the output of the solution storage unit is the third output of the device, the second and third inputs of the storage unit are communications are the second and third inputs of the microprocessor, respectively, the third and fourth inputs of the source data storage unit are the fourth and fifth inputs of the microprocessor, respectively, the second inputs of the first and second elements And are the sixth and My inputs of the microprocessor, respectively, the input of the remainder storage unit is eighth microprocessor input. ·