SU1399763A1 - Node processor - Google Patents

Abstract

The invention relates to computing and can be used in solving grid equations, to which second-order partial differential equations are reduced. The purpose of the invention is to increase speed. The delivered chain is achieved by the fact that a second decision unit 1 and a communication node 2 are entered in the node process containing the first decision unit 1, the data shift register 3, the coefficient memory unit 4 and the element 5. 1 hp f-ly 2 ill.

Description

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The invention relates to computing and is intended to solve grid equations, to which equations with second-order partial derivatives are reduced.

The purpose of the invention is to increase speed.

Pa figure 1 shows a diagram of the nodal processor; 2 is a control block diagram.

The node processor (FIG. 1) contains the first and second decision blocks 1, the communication node 2, the initial data shift register 3, block 4 of the coefficient memory, AND 5 and control block 6 in the grid processor.

Each decision block 1 includes two shifters 7 and 8, with +1 elements And 9, where c is the number of neighboring, node processors dp of the given node processor, (c + 2) is And the element 10 and adder 11.

Communication node 2 consists of an AND 12 element, a trigger 13 and an II-OR 14 element, which serve for a certain time to the next node processor of the next least significant solution code.

The grid processor contains a grid of nodal processors and a control unit 6.

The control unit 6 (FIG. 2) consists of the first 15, second 16 and third: 17 counters, trigger 18, first 19; second 20, third 21 and fourth I22 elements I.

: A grid processor is designed I for solving grid equations, to which I use second-order partial differential equations. The order of solvable ce exact equations does not exceed the number of nodal points of the grid processor. The nodal points, for example, of a flat grid processor, are located fS in the form of a flat uniform grid, between which adjacent nodes exist; two-way information communications. At each node, there is a node processor, which calculates the value of the function using the formula

jg

five

0

five

0

0 s

0

, j - nodal coordinates

processor; I is the free term of the equation.

The computational process is iterative in nature and ends when the maximum increment of the desired function from iteration to iteration becomes less than a specified value.

When solving practical problems that require a large number of nodal points, with an error determined by the value of the lower bit of the source data, it is required to operate with numbers whose size exceeds the size of the source data. This is due to the fact that in successive multiplications, when the result of the previous multiplication is used to obtain the next product, only the higher bits of the products are involved. The remaining minor bits of the products are discarded and are not involved in the calculations, as a result of which the calculation error increases rapidly. To reduce the calculation error of the need for P (IMO to increase the number of bits of the grid processor, however, this increases the time of the multiplication operation, and consequently, the time of the grid processor operation.

In the grid processor, the operations are performed with 2a-bit numbers and take into account the transfers that occur when adding the lower bits of the Over-bit partial sums of products. To reduce the computation time, the grid is divided into two layers by introducing into each nodal processor a second decision block 1 and a node 2 connection between the decision blocks 1. In the upper layer, the higher bits of the result are calculated. In the lower layer, in parallel, in time, the lower bits are calculated and the bits 2a are the discharge results, which are added to the results of the calculation of the upper grid layer in the next iteration. Due to the parallelization in time of computations, the time of one pore of the multiplication of a 2a-digit number is reduced by oi, times

TO.

4 ij, K;, j + q, 4,, j -, h,., + 0. К; - +

T .J-iJ-1

where K is the transfer coefficient;

H m., K, .j, 4-

d.

to (2n)

four,

where t is the time of one multiplication cycle.

When connecting b layers of the grid, the m calculation decreases b times.

Perform time-parallel multiplication for two iterations for two three-bit nodal processors, the transfer coefficients between them are the same and equal to K. In the first node processor, the product C Cf-K is calculated:

  ifi

"

O, K, K, j K,

time, K, q., K d., K, (f, -K, q.K, Cf, K, (f, K, (f, KI g, K,

Oj C (Sc Cj C || Cf Cg with

The mlady of the C CjC product bit of the product as it is formed is used in the second node processor to calculate a partial sum of the product D ' C:

 C K. I f 1 9 3 b K 4 2 4 Oe

D D.

... D, Dy Dg D, g ..,

In the second iteration in the first layer of the second nodal processor, the computation is the product

is

O, C, C, C,

bits D D 5 Dg, obtained in the first iteration. The result is the product of D O, the lower bits, but taking into account the transfers that have arisen in the calculation of these bits.

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about the issue of the re:

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The nodal processor operates as follows.

Register 3 and block 4 are alternately loaded with the codes of the initial information. A sequence of clock signals is output to the first input of control unit 6.

The computational process in the processor is iterative. At each iteration, another more accurate solution of the grid function is determined, the code of which at the end of the iteration is copied from the shifter - 7 to the shifter 8. Through the And 5 element, the information at the end of the iteration is outputted outside the processor for control. If at the selected nodal point of the processor, the increment of the code value by

If the 20 second outputs of decision blocks 1 become less than a predetermined value, the solution is terminated by blocking the output of clock signals to the first input of control block 6. During

25 each iteration is carried out in cycles to determine the next approximation of the solution. In each cycle, the next a-bit of the partial sum is determined for the cycles and then for the cycles

30, the transfers are completed and the upper partial bits of the partial amount are determined. The number p depends on the number of inputs of the adder 11. Thus, for the number of inputs of the adder 11, not exceeding 8,.

In control block 6, the following signals are generated.

From the output of the element And 19 is issued during the entire computational process a continuous series of shift signals

Q to the input of the shifter 7. From the output of the eleh

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45

50

oh m

55

Ment And 20 is given in one iteration cycle and the shift signals to the input of block 4 P 1m of these coefficients. From the inverse output of the trigger 18, upon completion of the shifts in the coefficient memory 4, the signal blocking the flow of information through the elements 9 and 10 to the inputs of the adder 11 is inserted. With the same signal, the counter 15 is reset, the lock is removed from the counter 16 and one is added to the contents of counter 17. Counter 16 provides an extension of the calculation cycle by p cycles required to complete the transfers in adder P. If a flat scale is simulated does not exceed 8 and the signal from the output of the fourth discharge stage is removed

Yes counter 16. With this signal, the trigger 18 is set in O, the code is shifted in the initial data shift register 3 and, through the AND 21 element, the code shift in the shift x.8.

Upon completion of the iteration cycles, the signal from the output of counter 17 blocks 1 operation of the element 21 and through element 22 enters the code from the outputs of the shifter 7 on the shifter 8, and also resets the counter 17. In the elements of the 10 input-related information on the corresponding coefficients. In the adder 11

The addition of the received | 5 input of the installation of the nodal processor is made

 product, At the beginning of each Cycle from the first output of the second block of block 1 through the element And 12 knot - L | a 2 links to the input of the adder 11 after | falls another bit of the corrective | sh | its code. In addition, from the output of the shifting generator, through the element I 9, to the input from the ummator I, the code H | astic sum of the sought solution enters the input, L-learned, during the previous iteration cycles. In the course of computations, the lower bits of the desired function are formed in the shifter 7 during the cycles, and the senior ones and the discharge functions are formed during the a-th cycle. At the beginning of each of the a-1 p | first cycles, the lowest-order bit generated by the function sought is fixed on the trigger 13 and delivered through the 2I-OR 14 element of the communication node 2 to the corresponding input of the second decisive block 1 of the neighboring nodal processors, during the second decade blocks 1 in the execution of the rf operation with a low-order bits

2a. Bit numbers. The results of the computation are 40 nodal processors, the second output of the desired function obtained on the first decision block is connected to

the first and second pe1, at the end of the iteration, dog; {1 engine 7 sending blocks are written to the shifters 8 of the same decision blocks 1. The code in the shift 8 of the second decision block 1 in the next iteration will be used as the correction code during the calculations in the first decision block 1 .

the second input element And, with the first decision block contains the first and second shifters, the adder and the group

45 pu of from + 2 elements And, and the first and second control inputs of the first decisive block are connected respectively to the recording and shift inputs of the first shifter, the output of which

Claims (2)

1. The node processor containing the shift register of the initial data, the coefficient memory block, the first decisive 6jioK and the element I, the input of the Hbtx outcome of the node processor data under the keys to the information inputs of the shift data of the initial data and the block the coefficient memory, the initial setup input of the nodal processor is connected to the write inputs of the initial data shift register and the coefficient memory block, the first synchronous input of the node processor is connected to the shift input of the initial data shift register, the first input of the mode attribute of the nodal processor is connected to the first control input of the first decisive block, the second synchronous input of the nodal processor is connected to the second control input of the first decision block, connected to a third manager. the input of the first decision block, the input of the attribute of the choice of nodes of the nodal processor is connected to the first input the element And, the output of which is connected to the output of the higher bits of the nodal processor result, from the first to the second (where c is the number of neighboring nodal processors for a given nodal processor), the information inputs of the higher bits of the nodal processor are connected respectively to the information. first to the first of the first decision block, the third synchronous input of the nodal processor is connected to the input of the counter of the memory of the coefficient memory, the output of which is connected to (c + 1) -th information input of the first decision block, the fourth sync the course of the nodal processor is connected to the fourth control input of the first decision block, the first video of the first decision block is connected to the output of the higher result bits the second input element And, while the first decision block contains the first and second shifters, an adder and a group of c + 2 elements And, the first and second control inputs of the first decision block are connected respectively to the write and shift inputs of the first shifter, the output of which connected to the first output of the first decision block, the third control input of the first decision block is connected to the first information inputs of the first and second shifters, from the first to the cth information inputs of the first decision block are connected respectively to the first inputs of the AND elements from the first to the cth group , (c + 1) -th information input of the first solver 71 the block is connected to the second inputs of the elements And from the first to the th group and the first inputs (from + 1) -th and (from +2) -th elements of the AND group, the fourth control input of the first decision block is connected to the synchronous input of the adder and to the input the shift of the second shifter, the output of which is connected to the second output of the first decision block, the second information input of the first shifter and the second input (from +1) of the AND group, outputs of the AND elements from the first to (from + 2), and the group are connected corresponding to the information inputs from the first to (c + 2) -and adder, the output of which It is connected to the second information input of the second shifter and the third output of the first decision unit, so that, in order to increase speed, a second decision unit and a communication node are inserted into it, the first controlling the input of the second decision block is connected to the first input of the mode attribute of the node processor, the second synchronous input of the node processor is connected to the second control input of the second decision block and the first control input of the communication node, the installation input of the node processor is connected to the third the control input of the second decision block and the second control from the first to the inlet of the communication node the information inputs of the lower bits of the nodal processor are connected respectively to the information inputs from the first to the second second decision block, (c + 1) -th information input of which is connected to the output of the coefficient memory block, the fourth control input of the second decision block is connected to the fourth synchronous input of the node processor, the output of the shift register of the initial data is connected to (c + 2) -th information input of the first s 0 5 o five 0 5 63 .8 the first decision block, (c - 2) and information and fifth control inputs of the second decision block are connected to the zero potential bus of the node processor, the fifth control input of the first decision block is connected to the first output of the communication node, the first and second information inputs which are connected respectively to the first output of the second deciding unit and the third output of the first decision unit, the second input of the mode attribute of the node processor is connected to the sixth control inputs of the first and second decision units, the second output y connection is connected to the output of the lower bits of the result of the nodal processor, while in the first and second decision blocks (c + 2) and information input, the fifth and pinch control inputs of the decision block are connected respectively to the second input (c + 2) -th element of AND group, (c + 3) -th information input of the adder and the third input (c + 2) -th element and group. 2. Processor according to claim 1, characterized in that the communication node contains an AND element, a trigger and an 2I-OR element, wherein the first control input of the communication node is connected to the first input of the AND element, to the trigger synchronization input, the first and second the inputs of the 2I-OR element, the second control and the first information inputs of the communication node are connected respectively to the installation input O of the trigger and the second input of the AND element whose output is connected to the first output of the node, the second information input of which is connected to the trigger information and the third the input element 2I-OR, the output of which is connected to the second output of the communication node, the output of the trigger is connected to the fourth input of the element 2I-OR. Fi.2