SU1545230A1 - Device for digital filtration - Google Patents

Abstract

The invention relates to computing, is intended to compute discrete conversion and perform digital filtering, and can be used in digital signal processing systems. The purpose of the invention is to simplify the device. This goal is achieved due to the fact that the device includes N-1 (N is the impulse response length or conversion dimension) of the computational modules, a memory unit, a permanent memory unit, a switch, a control unit, a clock generator, and a accumulator , adder, register, and corresponding links between device nodes. 4 il.

Description

The invention relates to computing, is intended for calculating the discrete Lurie transform and the filtering procedure and can be used in digital signal processing systems. The purpose of the invention is to simplify the device by reducing the hardware costs for the formation of weights.

Figures 1 and 2 depict a block diagram of a device for digital filtering; 3 is a functional block diagram of a RAM; 4 is a functional block diagram of the control unit.

The device (Figures 1 and 2) contains information input 1, block 2 of RAM, switch 3, information bus 4, block 5 of constant memory (weighting factors), triggers 6.id I, N-1), elements 2 AND

7.1, elements of NG 8.1, input registers 9.1, multipliers UL, adders ll.i, output registers 12.i, output adder 13, information output 14, register 15 of the first count, accumulating adder 16, output 17 constant component, 18 clock pulses, control unit 19, first device mode setting input 20, second device mode setting input 21, clock input 22 of control unit J9, clock output 33 of control unit 19, circulating output 24 of control unit 19, control mode control input 25 control output address 26 of control unit 19 , clock output G7 block 19 control, computational MODEPS 28.1, clock output 29 block 19 yi - ratios, bus 30 weight ktgMH-Fr, second address output 31 o-h 1 9 controls.

(L

WITH

The operation of the device when calculating the discrete Lurie transform.

The device evaluates the following expression:

NI

P 0

go / l a (n) wN

k - O, N-l, (1)

FW (k)

w,

nk

de a (n) are elements of the initial real vector jg of dimension N; the elements of the output vector of Fourier coefficients of dimension N;

weights; 15

 27) TH .GT1

e, j lN;

the number of the input sequence;

N is the dimension of the transform, 20, given by a prime number.

Imagine expression (1) in the following form:

1M25

Hut (n), (2)

"N

m

Lo)

FW (k)

-.m

where)

Fm (k)

(3)

am (0) + Fm (k), k-ltN-l,

i

is determined by the expression N-1k

 , k-l, N-l. (four).

We write the expression (4) in the matrix form and, having executed the corresponding permutations of, we obtain for N 5

In expression (5), the index of weighting factors was modulated by Module 5.

The cyclic structure of the matrix of weight coefficients in expression (5) makes it possible to significantly reduce the hardware costs for their formation.

For actual input data, expression (1) can be reduced to the form (3

(6) (7)

ReFm (k)

m

(k)

am (0) + ReFro (k), (k).

The terms ReFm (k) and IJ (k) in expressions (6) and (7) can be reduced to

type (5) with cyclic matrices j and, respectively.

Obviously, the difference between the calculations)

jg

15

20

25

.

thirty

35

40

45

50

55

T-, hrt, by the calculation of the values of ReF (k)

and

(AND)

T P rtl is that when calculating

the real parts of the second inputs of the multipliers, 10.1, will be given the real parts of the weight coefficients, and in the calculation of the imaginary part, the imaginary parts. The order of the input, output, and weight factors is identical. Therefore, in the future, we will consider), Fm (n), wn real numbers. Consider for example the calculation of one of the parts of the spectrum for N 5. Information in all registers and triggers is recorded by a positive sync signal. An upper logic level is applied to the input 20, which permits the passage of information from the first input of the switch 3 to the information bus 4. This mode corresponds to the DFT calculation. When calculating the convolution, the lower logic level arrives at the input 20. In this case, in the DFT calculation mode, the upper logic level, np input 21, corresponds to the calculation of cosine components, and the lower logical level - imaginary. For cosine components, adder 13 calculates the sum of the operands at its inputs, and from block 5, the bus 30 receives the actual values of the weighting factors. In computing the imaginary components, the adder 13 transmits the output of the operand from the output of the register 12.N-1, and from block 5 the imaginary components of the weighting coefficients arrive. The switching of the component coefficients is performed by the high output address 31, which is generated by the second control input 21.

We will describe the operation of the device with respect to inverse synchronization. The input samples are fed in a continuous stream to the input I of the device with the frequency of the clock generator 18. The RAM unit 2 reorders the sequence of input samples. Triggers 6.1 are synchronized with a positive forward clock pulse, all other registers with a positive inverse clock edge. The generator 18 clock pulses from the output of the sequence pr mogop51 51

pulse type meander. Ilformaya in blocks of the device corresponds to the time before the arrival of a positive front clock signal.

First beat At the input I of the device, the value of at + (0), on the bus 4 - 3 (1). Triggers 6.1-6.4 in the zero state. At the information input of trigger 6.1, a single value that is written in trigger 6.1 after half a cycle. At its input, a zero value is set from the output 27 of the control unit 19. On the tire weights the value of w. Through the element 7.1, the positive front of the inverse clock signal in register 9.1 will record the value of at (1). The register 15 does not receive a clock pulse and its contents do not change.

Second beat Pa input device 1 value (1); on bus 4 - a (2). At the entrance of the trigger 6.1 zero value. In the middle of a bar, a single value is written from the 6.1 E trigger.

trigger 6.2. On the tire weights w. In register 9.1, the value of a (1). Pa output of the multiplier 10.1 value 3 (1) w. At the output of the adder 11.1 the value of a (l) w. In accumulating adder 16, the value of a (1). Record information is sent to register 9.2. On register 15, the clock pulse is not received.

The third beat. At the input 1 of the device, the value (2), on the information bus 4, is aw (4). In the middle of a clock, the single value from trigger 6.2 is rewritten to trigger 6.3. At the entrance of the trigger 6.1 zero value. In the input registers 9.1 and 9.2 values) and at (2), respectively. In the register 12.1 value) w. At the outputs of adders 11.1 and 11.2, the values am (l) wu and am (l) w + 3 (1) w. There are 30 weight coefficients on the tire, the value of w. At the outputs of the multipliers 10.1 and 10.2, the values of at (1) 4 and am (2) wi, respectively. On register 15, the clock pulse is not received. In the accumulating adder 16, the value of at (1) + at (2).

The fourth beat. At the input 1 of the device value (3), on the information bus 4 -). In the middle of a clock cycle, a single value from flip-flop 6.3 will be overwritten by flip-flop 6.4 to issue a clock pulse to register 9.4. At the input of the trigger 6.J zero. In the input registers 9.1-9.3 value2 Ю6

neither am (1), am (2), lgp (4) COPTIUM g is gnenno. On the bus 30, the weights are ko ("bitwise w value. On the outputs of the multipliers 10.1-10.3, the values am (l) w4, am (2) w4, a (4) w, respectively. In registers 12.1 and 12.2, the values are a (I) w + arn (2) w, respectively. At the outputs of adders 11.1-11.3, otherwise 0, 3 (1) w2 + am (2) w4 and

am (l) w + a T1 (2) w 2 + am (3) and e, respectively. The register 15 does not receive a clock pulse and its contents do not change. In accumulating adder

5 16 the value of am (l) + am (2), a (4).

Fifth time. At the input 1 of the device a | T14 (4), on the information tin 4 - 3 (0). In the middle of the clock, the trigger 6.4 will record a zero value, and the trigger value 6.1 will receive a single value. In the input registers 4.1-9.4, the values of a (1), a (2), am (4), and (3), respectively. On the bus 30 weight coefficients value v. On

the output of the multi-empels 10.1-10.4 znlcheR 1 / 1H H / 0 fn Y / / 1

nor a (l) w5, a (2) w% a (4) wi, a (3) v, respectively. In registers 12.1- 12.3, the values am (l) w4, am (l) w7 + aw (2) v, 3 (1) w + am (2) w2 +

0 + arri (4) w respectively. At the outputs of adders M.1-11.4, the values am (l) w3, + am (2) w3, am (l) v + + ani (2) w4 +) 3, am (l) wp + + aM (2) wa + aw (4) w4 + aw (3) w3 F (1)

5, respectively. On register 15, a clock pulse at the end is also the same. R accumulative adder 16 is at (1) + at (2) + a | 1 (4) + at (3). From output 29 of the control unit 19 of the syncro pulse there is no pulse.

The sixth beat. Similar to the first tact. At the input 1 of the device a (O), on the information bus 4 - AGT11 1 (1). In the middle of a bar is a single value.

5 from the output 27 of the control block 19 is written to the trigger 6.1. In the remaining 6.1 triggers, the values are zero. In the second registers 9.1-9.4 the information has not changed. On the bus 30 value

one

0 w. The contents of the registers 12.1-12.4 and the results at the outputs of adders 11.1-11.4 and multipliers 10.1-10.4 have not changed. In register 15, the value of a (0). In accumulating adder

5 16 the value of at (1) + at (2) + aw (3) + + 3 (4) + at (0) Fm (0), which is removed from the output in the first half of the cycle. In the second half of the accumulate cycle, the adder 16 is zeroed.

ten

15

The samples (tp + 1) of the input array are processed similarly to the previous one.

Seventh tact. Analogous to the second measure. At the outputs of adders 11.2- 11.4, the values am (l) w3 + am (2) v + am (2) w3 +, + a (2) w4 + a ™ (4) (3) w F ™ (2).

At the outputs of the multipliers 10.2-Sh.4, the values of arn (2) w (, am (4) w, am (3) w, respectively. On the tire 30 weight

a

coefficients w. In registers 12.1- 12.4 values) w, am (l) w + + nam (2) w3, am (l) w2 + arn (2) w4 + arn (4) v F (1), respectively. The value of F (1) is fed to the first input of the adder 13. The second input of the adder 13 receives the value). If the device calculates the real hour of the spectrum, then at output 14 of the adder i there will be the value Frn (l) Fm (l) + am (0) If the device calculates the imaginary part of the spectrum, then the adder 13 performs the operation F (1) F ( O. The control of the 25 mats output adder and the adder 13 is realized by the potential at the input 21 of the device.

The eighth cycle is similar to the third cycle. On the bus 30 w4 value. The multipliers 10.3 and 10.4 give the values of a ™ (4) w2 and am (3) wa. The samples (ha + 1) of the array are processed similarly to the third clock cycle. At the outputs of adders 11.3 and 11.4, the values of am (l) w +

When implementing a digital filtering procedure, the device calculates the filter output samples in accordance with the expression

N-u

x (k) XLa (k-n) h (n), (8)

where h (n) - coefficients of the impulse response of the filter; and (n) - input signal samples. When operating in digital filtering mode, control input 20 receives a low signal level, which ensures that all 6.1 trigger devices are set to one. This ensures that information is recorded in register 9.1 with each clock cycle. The connections between the second inputs of the multipliers 10.1 and the bus 30 are broken. Pa second inputs of the multipliers 10.1 receive the coefficients of the impulse response. The control input 21 is given a signal permitting the transfer of information from the output of the register 12.N-1 to output 14, from which it will be removed in each case) b (h filtered value x (k)).

Claims (1)

30 claims 20 + am (2) wr + am (4) w2 u) x / + am (2) L35 +) 1 / + am (3) w U Fm (4), respectively. In registers 12.2-12.4, the values am (l) w3 + am (2) w 3 (1) v + + a (2) v3 + am (4) w, am (l) wz + am (2) w4 + + am (4) w3 +) 1 Fm (2). Similarly to the previous clock cycle from the output 14 of the device, the value F (2) is taken. The ninth measure is similar to the fourth measure. The output of the multiplier 10.4 A device for digital filtering containing (Nl) (N is the impulse response length) of the number of modules, control unit and clock generator, the output of which is connected to the clock input of the control unit and the first clock input of the 1st (, N-1) computing module, information output of the j-th (j - 1, N-2) computing module is connected to the first information input (j + l) -ro of the computing module, the second clock input of which is 50 am (3) w4 value. At the output of the totalizer 45, it is connected to the clock output (j-1) - pa 11.4 value + a (2) w + + am (4) w2 + am (3) w4 Fm (3). In registers 12.3 and 12.4, the values + + am (2) v / + am (4) w 2- and am (l) w4 + + am (2) w3 + am (4) w1 + am (3) w3 Fm (4 ). Analogously to the previous clock cycle from output 14, the value of F (4) is taken. The tenth bar is the same as the fifth bar. In register 12.4, the value of a (l) w3 + a (2) w + a (4) + a (3) w4 Fm (3). At output 14 of the device, the value of Fm (3). Further operation of the devices, i, is continued according to the described algorithm. 55 first computing module, the first and second clock outputs of the control unit are connected respectively to the second clock input of the first computing module and the third clock input of the 1st computing module, and the 1st computing module contains the element NOT, the first and second registers, adder, multiplier, element Both and the trigger, the output of which is the clock output of the computing module and connected to the first input of the AND element, the output of which is connected to the clock input r 0 five 5 matsin output adder When implementing a digital filtering procedure, the device calculates the filter output samples in accordance with the expression N-u x (k) XLa (k-n) h (n), (8) where h (n) - coefficients of the impulse response of the filter; and (n) - input signal samples. When operating in digital filtering mode, control input 20 receives a low signal level, which ensures that all 6.1 trigger devices are set to one. This ensures that information is recorded in register 9.1 with each clock cycle. The connections between the second inputs of the multipliers 10.1 and the bus 30 are broken. Pa second inputs of the multipliers 10.1 receive the coefficients of the impulse response. The control input 21 is given a signal permitting the transfer of information from the output of the register 12.N-1 to output 14, from which it will be removed in each case) b (h filtered value x (k)). 0 30 claims A device for digital filtering containing (Nl) (N is the impulse response length) of the number of modules, control unit and clock generator, the output of which is connected to the clock input of the control unit and the first clock input of the 1st (, N-1) computing module, information output of the jth (j - 1, N-2) computing module is connected to the first information input (j + l) -ro of the computing module, the second clock input of which is connected to the clock output (j-1) - go is connected to the clock output (j-1) - first computing module, the first and second clock outputs of the control unit are connected respectively to the second clock input of the first computing module and the third clock input of the 1st computing module, and the 1st computing module contains the element NOT, the first and second registers, adder, multiplier, element Both and the trigger, the output of which is the clock output of the computing module and connected to the first input of the AND element, the output of which is connected to the clock input r register, the output of which is connected to the first input of the multiplier, the output of which is connected to the first input of the adder, the output of which is connected to the information input of the second register, the output of which is the information output of the computing module, the first information input of which is the second input of the adder, the first setup input the trigger is the first clock input of the computing module, the second clock input of which is the second setup input of the trigger, the information input of the first register is the second information input of the computing module, the third clock input of which is the input of the element NOT, the output of which is connected to the second input of the element AND and the clock input of the second register, and the second input of the multiplier is the input of the calculation of the coefficient of the computing module, characterized in that in order to simplify the device, it contains a memory block, a fixed memory block, a switch, an adder, a register and an accumulating adder, the output of which is the output of the constant component of the device, The input of which is interconnected is the first information input of the switch and the information input of the memory block whose output is connected to the second in0 five 0 five 0 five the switch input of the switch, the current of which is connected to the second information input of the 1st computational module, the input of the task of the command card of which is connected to the output of the permanent memory unit, the address input of which is connected to the first address output of the control unit, the second address output of which is connected to the address input of the memory unit, the control input of the switch is connected to the first input of the mode setting of the control unit and is the first input of the device mode setting, the second input of the mode setting of which is with interconnected second input of the control unit mode setting and - synchronization input of the adder, the output of which is the information output of the device, the third clock output of the control unit is connected to the clock input of the register, the output of which is connected to the first information input of the adder connected to the information output (Nl) -ro of the computing module, the output of the zeroing of the control unit is connected to the input of the zeroing of the accumulating adder, the information input of which is connected It is connected to the information input of the register and is connected to the output of the switch, and the output of the clock generator is connected to the clock input of the accumulating adder. Output I  and; C5 "Mi J. i -EL Ji Mp G2 { cmi / g ft / e flw26 flw.J / W g CHA    A A AA (t ). 2J | l f l “. (/ R2 Ultrasound ffllF 1t 01 - No J 2 27 2S h