SU1721612A1 - Matrix operation system - Google Patents

Abstract

The invention relates to computing and can be used in high-performance specialized computers and signal processing devices for solving systems of linear algebraic equations and calculating the first eigenvalue and matrix vector. The purpose of the invention is to expand the functionality by calculating the first eigenvalue and the corresponding eigenvector. This goal is achieved by the fact that the device for operations on matrices contains n computational modules of the first type 9, where n is an order of the systems of linear algebraic equations, a computational module of the second type 10 and an output unit 11. 4 ill., 2 tab.

Description

The invention relates to computing and can be used in high-performance specialized computers and signal processing devices to solve systems of linear algebraic equations and calculate the first eigenvalue and the first eigenvector of matrices.

A device is known for solving systems of linear algebraic equations containing 2n-1 computational modules (VMs), where n is the order of the system of linear algebraic equations, 2n-1 blocks of data and the output unit 1.

A disadvantage of this device is the impossibility of calculating the first eigenvalues and vectors of n × n matrices.

The closest in technical essence to the proposed device is

for solving systems of linear algebraic equations, containing p VM, an output block and a register, each VM containing three registers, a multiplier and an adder, a block of 2-output registers, n calculators, n comparison nodes, two And elements, and a trigger 2.

A disadvantage of the known device is the impossibility of calculating the first eigenvalues and the vectors of the nx matrix.

The purpose of the invention is to expand the functionality of the device by calculating the first eigenvalue and the first eigenvector of the matrix.

Figure 1 shows the structural diagram of the device; figure 2 is the same for case n 3; on fig.Z and 4 - functional diagrams of computing modules.

Vj

| sj

About N

The device (FIG. 1) contains a group of information inputs 1, the first 2, the second 3 and the third 4 data inputs, the input 5 sets the calculation error, the synchronous input 6, the first 7 and the second 8 configuration inputs, the computing modules 9 and 10, the output block 11, information outputs 12 and output 13 of the sign of the termination of calculations.

Computing module 9 (FIG. 3) contains the first 14, second 15 and third 16 information inputs, the synchronous input 17, the first 18, the second 19 and the third 20 registers, the multiplier 21, the adder 22, the first 23 and the second 24 information outputs.

The computing module 10 (FIG. 4) contains the first 25, second 26 and third 27 information inputs, the first 28 and second 29 tuning inputs, the synchronous input 30, the first 31 and second 32 registers, the first 33 and second 34 triggers, the calculation node 35 the reciprocal of the number, the first-sixth groups of 36-41 elements AND, the first 42, the second 43 and the third 44 groups of elements OR, the first-fifth elements AND 45-49, the element NOT 50, the multiplier 51, the first 52 and second 53 information outputs .

The basis of the operation of the device when calculating the first eigenvalue of AI and the corresponding eigenvector XT for some initial approximations of the components of the eigenvector and eigenvalue xj. ha, and Ai put formulas

x (0Vi

n - 1

hg

-t- (2 aijxj + ain), xn 1,1 1,2n-1;

A1 j 1

n -1

L-1 2 SnjXj + 3nn. j -

To calculate the xpk and Ark values, the Zeydel iterative method for solving systems of linear algebraic equations is used, in which the xi and AI values are determined by the recurrence relations:

Xi (o), (o) x. (O) .Xn (o), (o) 1.

. (i) J / xW, (i-o /; V

/ c. |)

a; .j-U) Xj -; + nJ4 1,., ...;

, (0

50

lQj, n-i + i + ixB.i, j ,, K.w1 ... j

xi (k) Xj (k) (n), i TjPF, k 1,2, ...; Xp (.55

A1 (S, 0) Xn (k). (J). XnfrMM) +. T7; AlM, AlM, (n) Xn (H, M

0

5 0 5

0

five

0

five

0

five

The accuracy of calculating the values of xi and AI is determined by the value of e. If the differences Axl xj (k + 1) -xi (k) () H AAi A / k + 1 - A / k satisfy the condition IA xi I c, lAAil, then can be taken approximately xi "(x2 (g), xn-i (k + 1l 1) and Ai" Ai +4

Consider the work of the computing module 1.0 (figure 4), the logic of which is given in table 1. Computing module 10 operates in four modes.

In the first mode of operation, zero inputs are given to the tuning inputs 28 and 29, which set push-pull triggers 33 and 34 to the zero state, and a single signal is generated at the output of the And 47 element, which opens a group of And 37 elements. In this case, the x value written to the register 31, through the group of elements AND 37, the group of elements OR 42 and 44 is fed to information outputs 52 and 53.

In the initial mode of operation, the tuning inputs 28 and 29 are respectively zero and single signals, which set the triggers 33 and 34, respectively, to zero and one states. The inputs 26 and 27 are continuously supplied respectively with AG0 and the unit number. The group of elements AND 36 opens, through it the value x recorded in register 31 is fed to the input of the group of elements OR 42 and respectively to output 52. In addition, through the open group of elements AND 39 the unit number is fed to the input of the group of elements OR 44 and to the output 53. A single signal is generated at the output of AND 46, which opens an AND 38 group of elements. At the falling edge of the clock pulse, the value A Ai fed through the AND 38 group of elements and the OR 43 group of elements is written to register 32 (AND 48 is opened and permits passage th clock pulse on a clock terminal of register 32).

In the third mode of operation, the setup inputs 28 and 29 are supplied with single and zero signals, respectively, which set the triggers 33 and 34, respectively, to the single and zero states. At the same time, a single signal is generated at the output of AND 49, which opens a group of elements AND 40. At the output of the node calculating the reciprocal of the number 35, the value 1 / A is formed, and at the output of the multiplier 51, a value - x, which, through the group of elements 40, elements OR 42 and 44 are fed to outputs 52 and 53.

In the fourth mode of operation, the setup inputs 28 and 29 are given single signals, which set the triggers 33 and 34 to one state. At the output of the element 45, a single signal is formed, which opens a group of elements 41. The value A ™, fed to input 25, through the group of elements 41 and the group of elements OR 43 is fed to the information input of the register 32. Since the element 48 is open, the value A on the trailing edge of the clock pulse is recorded in register 32. The value A from the output of register 31 through an open group of elements AND 36 and through a group of elements OR 42 is fed to output 52. A single number through an open group of elements AND 39 and a group of elements OR 44 is fed to output 53 .

When describing the operation of the device in the designation, the first index in brackets (k) indicates the iteration number, and the second index in brackets (j) indicates the number of the recurrent step for the kth iteration. In the notation x k 1, the index in brackets (k) indicates the number of the iteration, and the index t without brackets indicates the number of the device operation cycle.

Consider the operation of the device for case p. 3. Input 2 is supplied with the values xi, X2 and 1, respectively, on the zero, second and fourth cycles, and on subsequent cycles, zero values are supplied. The inputs 3,4 and 5 are continuously supplied with the values of AI, 1 and соответственно, respectively. The organization of feeding the input stream of elements to the inputs 1i (i 1,2,3) and the control signals to the inputs 7 and 8 is shown in FIG. 2. The operation of the device according to the cycles is explained in Table 2, in which the values at the inputs, the states of the registers, the triggers and the values at the outputs of the computational modules 9 and 10 are given.

On the ninth, eleventh, and thirteenth clock cycles, xr1, w, and Ar, respectively, are formed in the computing module 10, which are written to the registers of the output unit 11. On the fifteenth, seventeenth and nineteenth cycles in the computing module 10, X2 and Ag2 are formed, respectively, which are also written to the registers of the output unit 11. At the twentieth cycle in the output block 11, the condition iAxil Ј and lAAil E is checked. If the condition for all Xi-x values, (i 1,2) is fulfilled, then at output 13 there is a sign of the end of the calculations a 1 and from outputs 12i and 122, the first and second components of the first eigenvector xi (xi, x2.1) are output, respectively, and from the output 12, the value of the first eigenvalue AL If

the sign of the end of computation a 0, the iterative computation process continues. The delivery of correct results xi and AI is provided with a block 11 and 5 at the moments of time t n + 2n (k + 1),

Where to 1,2,3 In the remaining moments

time t s n + 2n (k + 1), information from outputs 12 is not retrieved. When solving systems of linear algebraic equations, the tuning inputs 7 and 8 are supplied with zero signals, the computing module 10 performs the function of delaying information arriving at its first information input 25 by one

5 tact. The values of the roots of the equations xi (i 1, n) are taken from the outputs 12i and 1 at the moments

time t n + 2n (k + 1), k 1,2,3

Claims (1)

The invention The device for operations on matrices containing (n + 1) a computational module (p is an order of a system of linear algebraic equations) and an output unit, the first information input of the device connected to the first information input of the nth computation module, the first information input the i-ro input of the computation module (, p-1) is connected to the first information output (i + 1) -ro of the computation module, the first information output of the first computation module is connected to the first information input of the (n + 1) -th computation the first information output of which is connected to the first information input of the output unit, the second information output of the (n + 1) th computing module is connected to the second information input of the first computing module, the second information output of the i-ro computing module is connected to the second information input (i + 1) -ro of the computing module, jth information input of the device input group (j 1, p) is connected to the third information input of the j-ro computing module, the input of the calculation error of the device wa is connected to second data input of the output unit, the clock device is connected to the clock terminal of all the computing modules and output unit, computing the output feature termination is connected to the output device eponymous j-th output block of data output is the output of the same name, 5 characterized in that, in order to expand the functionality of the device by calculating the first eigenvalue and the first eigenvector of the matrix, the second and third in0 five 0 the formation inputs of the device are connected respectively to the like inputs of the (n + 1) -th computational module, the first and second tuning inputs of which are the same inputs of the device, and the computing modules from the first to the 5th are capable of realizing the following functions: Aj + 1 aj bj + cj, AT i + 1 hi bj, where a, s, and c are the values at the third, second, and first information inputs of the computing module at the J-M cycle, respectively; A and B are the values at the first and second information outputs of the computational module, respectively, at the J-M cycle; (n + 1) -th computing module is configured to implement the following functions: AJ + 1 Bj +1 0 five Where S 0 fxj1 / bj if (d, /) (1,0) Y, if (o1, $ (0,0X0,1X1.1) xj, if (d, (0,0X1,1) 1 if (d, ft) (0,1) xJ1 / bj if (d, /) (1,0) (c. if (,) (0,1) x, if (, p) (1.1) d and j $ are the values at the first and second tuning inputs of the computational module, respectively, at the jth cycle; x and c are the values at the first and second information inputs of the computation module at the jth cycle, respectively; A s s are the values respectively at the first and second information outputs of the computing module at the jth cycle.   and c a 1 one t "x ®UZ3 FIG. four. Editor I. Shmakov Compiled by V. Yakush Tehred M. Morgental G77 I, I and Proofreader M. Demchik