SU1631556A1 - Arithmetic device for fast fourier transform processor - Google Patents

Abstract

The invention relates to computing and is intended to build real-time signal processing devices. The purpose of the invention is to increase speed. This goal is achieved due to the fact that the device includes multipliers 1-4, switches 5-9, trigger 10, adders 11,12,13, subtractors 14,15,16, adders-subtractors 17,18, registers 19- 22 and the element NOT 23. 4 Il.

Description

About zh

yuuuj / c i It is the umuCnlCH K LISTEN TECHNOLOGY and is designed to build signal processing devices that operate in real time.

The purpose of the invention is to increase the speed of the device when processing complex-coupled input data.

The analytical expression of the algorithm for calculating the Fourier transform coefficients of the complex-conjugate input data can be represented as

n - 1 n -2 (P CkTk P &) X, k - ok - o

0)

15

where F (f0, fi, f2fN-i) T is the vector of the Fourier transform coefficients;

X is a vector of input data with the property of complex conjugation, which can be expressed as

Xi

I 1.M / 9-1,

Where

complex conjugation symbol;

X0, Hm / 2 are pure real numbers;

N is the dimension of the transform.

The remaining terms of expression (1) are described by the formulas:

, p -k - 1

 W2 ® I 2k

 V h k + 1

(2)

Tk | 2 n - k - 1 v 2 k + 1: (3)

  |) | ® Mf k PT2 p - k, (4)

where 1G is the unit matrix of dimension;

A / 2 is a Fourier transform matrix of dimension two;

& - the Kronecker matrix symbol;

I is the transposition symbol;

V 9k + 1

I 9k Oh

D ok

, nk -1

0

n - k - 1

45

where D is a diagonal matrix containing purely real diagonal coefficients:

P is the ideal permutation matrix;

S - right circular matrix of the form

g t0 0 ... 0 g

 0 ... 0 0

000 gt 0

00 0 ... g g

(five)

55

0

five

0

five

The q element of the matrix S is described by the expression g 1 + j (L., where a is a number equal to the base of the number system to be used; j 1.

The calculation of the Fourier transform using formula (1) is performed in two steps. At the first stage, the input vector X is multiplied by block-diagonal matrixes b. The result of this step is a vector of intermediate data X. whose elements are real numbers.

In the second stage of algorithm (1), iteration of the calculation is performed, similar to the classical fast Fourier transform algorithm, with the only difference that all operands and coefficients are pure real numbers.

The basis of the computational cost at the first and the second stage of the calculation is the procedure of multiplying the intermediate data vector X or its part by the matrix S of the form (5), and the result of this multiplication is indicated by the vector Y, and its elements are represented as

Yi gXi + g X m

(6)

Where

m means reducing the number of

0

five

0

five

0

five

modulus t;

t is the dimension of the matrix S; Xi and X are elements of the vector X. Denote Xi by B, and X by C

as a result, expression (6) takes the form

ReYi ReB + ReC-a (lmB - ImC);

lmY, ImB + lmC + «(ReB - ReC), (7) where Im and Re - denote the imaginary and real parts of the number.

The relation. (7) should be interpreted as an analytical expression of the basic operation of the first stage of the algorithm (1) for calculating the Fourier transform.

At the second stage of calculation, using the formula (1), a butterfly-type sequence of operations is performed:

AJ X, + Chi-1 di:

Am XI - HN- rdi, (8)

where Ai, Am are the results of a butterfly operation;

di is an element of the real diagonal matrix D;

Xi, Xj + i are elements of some intermediate data vector.

Combining the four operations (8) (two operations from two adjacent iterations of the computation) with N 49 yields an enlarged basic operation, which requires four output operands XxX2, Xs and XA and three coefficients di, d2 and da.

Figure 1 is given a functional diagram of the proposed device; Fig. 2 is a graph calculating the fast Fourier transform for N 16; FIGS. 3 and 4 show basic operation structures in accordance with expressions (7) and (8).

The device (figure 1) contains multipliers 1-4, switches 5-9, trigger 10, adders 11-13, subtractors, summation-subtractors 17 and 18, registers 19-22, element HE 23, inputs 24-30, clock input 31, mode setting input 32 and information inputs 33-36.

The device works as follows (Fig.2-4),

In accordance with the calculation graph of the discrete Fourier transform (Fig. 2), the sequence of basic operations of Fig. 3 is first performed.

For this purpose, the device level signal O is applied to the device input 32, which is fed to the address inputs of the switches 5 and 6 and puts them into data transfer mode from the first inputs to the outputs. In addition, the level signal O arrives at the control input of the first adder-subtractor 17 and transfers it to the data subtraction mode. The arrival of the specified signal at the input of the element HE 23 inverts it, as a result, the high level signal from the output of the element NOT 23 arrives at the control input of the second adder-subtractor 18 and transfers it to the addition mode of the operands.

In the first cycle of operation of the device, the real parts of the first and second operands of the basic operation of FIG. 3 are fed to the inputs 24 and 25, and the imaginary parts of the first and second operands, respectively, are fed to the inputs 27 and 28. After a time equal to the execution time of the addition operation and the propagation time of the signal through the switch, the outputs of the adder 11 and the subtractor 14 form the results of the addition and subtraction of the real parts of the first and second operands of FIG. 3, which is provided to the real part the first operand from the input 24, and to the other inputs of the first adder 11 and the first subtractor 14c of the input 25 of the device through the input of the first switch 5 - the real part of the second operand.

Similarly, the outputs and totalizers 17 and 18 form the difference and the sum of the imaginary parts of the first and second operands of FIG. 3, respectively. By the end of the first cycle of operation of the device, this allows the sum and difference of the real parts of the first and second operands to be applied to the inputs of registers 19 and 20, and the difference and the sum of imaginary parts of the first and second operands of the basic operation of FIG. 3 to the inputs of registers 21 and 22.

Upon the arrival of a clock pulse at the clock inputs of the indicated registers, the operands in the inputs are written to them, and the inputs 24,25.27 and 28 receive the input operands of the basic operation of FIG. 3 as described.

In addition, the arrival of a clock pulse to the clock input of the trigger 10 at its output sets the level signal O, received at its input in the first cycle of the device. The level signal O from the output of the trigger 10 goes to the control inputs of the switches 7.8 and 9 and translates them in the mode of data transfer from their inputs to the outputs.

This allows for the second cycle of operation.

devices at the output of the adder 13 to get the result of adding the sum of imaginary parts to the input of the adder 13 from the output of the register 22 through the input of the switch 9, and the difference

parts entering the adder 13 from the output of the register 20 through the input of the switch 7.

Real Part Difference Code

input operands arrive at the input of switch 7 with a shift by K bits, which are determined by the value of the trivial factor a. The output of the subtract 15 forms the difference between the sum of the real parts of the first and second operands of the base operation of FIG. 8 At the same time, at the input of the switch 8, the operand is multiplied by a factor a in accordance with the structure of the basic operation of FIG. Thus, to

At the end of the second cycle of operation of the device at the outputs of the adder 13 and subtractor 15, respectively, the imaginary and its integral parts of the result of performing the basic operation of FIG. 3 are formed, which arrive at the outputs 34 and 35 of the device, and the inputs of the registers 19-22 are fed . On the positive differential of the next clock pulse to the inputs 24.25,27

and 28 devices receive new values of the initial operands of the basic operation of FIG. 3, intermediate results of the basic operation are entered into registers 19-22, and the results of calculations are read from the outputs 34 and 35 of the device.

Upon the arrival of subsequent clock pulses, the actions described above are repeated by analogy until the completion of the first stage of the calculations using algorithm (1).

On the last cycle of performing the basic operation of FIG. 3, the inputs of the registers 19-22 are intermediate results of performing this basic operation. With the arrival of the next clock pulse, the indicated intermediate data is recorded in registers 19-22, the imaginary and real parts of the output operand of the basic operation of FIG. 3 are supplied to the device outputs 34 and 35, and the first and second operands of the basic operation of FIG. 4 are input to inputs 24 and 25. , to the inputs 26-29 of the device, respectively, the first coefficient, the third and fourth operands, the second coefficient of the basic operation of FIG. 4.

In addition, a level 1 signal is input to the device 32, which is fed to the control inputs of the switches 5 and 6, the input of the element NO 23, the control input of the subtractor 17, and the input of the trigger 10.

This leads to the setting of switches 5 and 6 in the data transfer mode from input to output, the adder-subtractor 17 - in the addition mode of operands, and the adder-subtractor 18 - in the subtraction mode.

In multipliers 1 and 2, the second and fifth operands of the basic operation of FIG. 4 are multiplied by the first and second coefficients, respectively. The results of these multiplications from the outputs of multipliers 1 and 2 through the inputs of switch 5 and 6 are fed to the inputs of adder 11, subtraction 14 and adders-subtractors 17 and 18.

At the same time, the first operand of the basic operation of FIG. 5 of the input 24 of the device enters the inputs of the adder 11 and the reader 14, and the third operand of the basic operation of FIG. 4 comes from the input of the device 27, which allows the outputs adder 11 and subtractor 14, as well as adders-subtractors 17 and 18, to obtain intermediate results of performing the basic operation of FIG. 4.

At the same time, at outputs 34 and 35 of the device, the results of performing the basic operation of FIG. 3 are formed.

The duration of the considered device operation cycle differs from the duration of the previous device operation cycles at the first stage of the algorithm (1) and is equal to:

1i - ten + tyM + Tk,

where ten, tyM, Tk are the times of performing the operation of adding, multiplying, and spreading the signal through the switch.

Thus, after a time equal to tM, after the arrival of the last clock pulse, the next clock pulse arrives at the device input 31, according to which

intermediate results of calculating the basic operation of FIG. 4 are recorded into registers 19-22, the results of performing the basic operation of FIG. 3 are output to the device outputs 34 and 35, the input operand device inputs 24-29 (by analogy with that described above), and input 30 of the device - the third coefficient of the basic operation of figure 4. In addition, a level 1 signal from the device input 31 is recorded in trigger 10 and

enters the control inputs of the switches 7,8 and 9, which puts them in data transfer mode from the inputs to the outputs. As a result of the latter, the device structure is configured to perform basic

operations of FIG. 4, which allows, after a time equal to the outputs of the adders 12 and 13, as well as the outputs of the subtractors 16 and 15, to obtain the results of performing the basic operation of FIG. 4. At the same time in multiplier x 3

and 4, the results of multiplying the third and fourth intermediate results of the basic operation of FIG. 4 by the third coefficient are obtained. These multiplication results through the inputs of the switches 8 and 9 are fed to the inputs of the adder 12, the subtractor 15 and the adder 13, the subtractor 16, respectively. The other inputs of the adder 12 and subtractor 15 receives the intermediate result from the output of the register 19, and the inputs

the adder 13 and the subtractor 16 supply the intermediate result of the calculation from the output of the register 20 through the input of the switch 7.

Upon the arrival of the next clock pulse at the input 31 of the device to the inputs 33-36

the device receives the results of the basic operation of FIG. 4, the intermediate results of the basic operation of FIG. 4 are entered into the registers 19-22, and the source operands of the said basic operation are input to the inputs 24-30 of the device.

At subsequent stages of operation, the device performs the basic operations of FIG. 4, after which it can be switched to

perform basic operations fig.Z.

Claims (1)

An arithmetic unit for a fast Fourier transform processor comprising first, second, third, and fourth multipliers, two adders, two subtractors, two adders, subtractors, two switches and four registers, with the output of the first switch connected to the first inputs of the first adders and The outputs of the second adder and the subtractor are respectively the first and second information outputs of the device, characterized in that. that, in order to increase speed, the third, fourth and fifth switches, the third adder, the third subtractor, the trigger and the NOT element, whose output is connected to the control input of the second adder and subtractor, the output of the first adder are connected to the information input the first register, the output of which is connected to the first inputs of the second adder and subtractor, the output of the first subtractor is connected to the information input of the second register, the output of which is connected to the first information input and shifted to K bits ( K is an integer) to the second information input of the third switch, the output of which is connected to the first inputs of the third adder and subtractor, the outputs of which are respectively the third and fourth information outputs of the device, the first information input of which are interconnected second inputs of the first adder and subtractor , the output of the first adder-subtractor is connected to the information input of the third register, the output of which is shifted by K bits connected to the first information input quarter switch and the first input of the third multiplier, the output of which is connected to the second information input of the fourth switch, the output of which is connected to the second inputs of the second adder and subtractor, the output of the first multiplier is connected to the first information input of the first switch, the second information input of which is connected to the first input of the first multiplier and is the second information input of the device, the third information input of which is interconnected second information inputs of the first and the second adders-subtractors, the output of the second adder-subtractor is connected to the information input of the fourth register, the output of which is connected to the first information input of the fifth switch and the first input of the fourth multiplier, the output of which is connected to the second information input The fifth switch, the output of which is connected to the second inputs of the third adder and subtractor, the output of the second multiplier is connected to the first information input of the second switch, the second information input of which is connected to the first input of the second multiplier and the first and second inputs of which are the second entrances respectively, the first and second multipliers, the second inputs of the third and fourth multipliers are interconnected and are the third input of the device coefficient, the clock input of which are interconnected clock inputs of the first, second, third and fourth registers and a trigger input of the trigger, the output of which is connected to the control inputs of the third, fourth and The fifth switch, the control inputs of the first and second switches, the first adder-subtractor, the input element NOT and the setup input of the trigger are interconnected and are the input of the task device mode. seh | 2 o -.-.- I. -. s - g  I | ь 14 (41 1 14 1 IX Ix if (4 .ЧЧЧЧ vw k ,, t. I seh mh | 2 o -.-.- I. -. s - g  14 1 IX Ix if (4 t. I N I  5 S3 1Q "  g g Re In FIG. 3 X ImA