SU1424017A1 - Apparatus for computing integral operators - Google Patents

Abstract

The invention relates to digital computing and is used to solve the Volterra-Hammerstein integral equations in problems of GP / 71fj related to the calculation of the signal flow in the communication lines, heat transfer, etc. The aim of the invention is to improve the accuracy of calculations and speed. The device contains a register of 1 step, the first block of elements AND 2, the first accumulating adder 3, the first block of comparison 4, the register 5 of the limit value, the second and third blocks of elements AND 6, 7, the block 8 for calculating the equation frame, the fourth block of elements And 9, the second accumulating adder 10, block 11 calculating the integrand function, first multiplying unit 12, second comparing unit 13, second multiplying unit 14, OR 15 element, NOT 16 element, first switch 17, Fifth block of AND elements 18, delay element 19, block 20 shift, the second switch 21, the sixth block lementov AND 22, OR block elements 23, the third accumulator 24, 2 yl. "FC-W | X (L 4 1C 4

Description

The invention relates to digital computing and can be used as part of a specialized computing device for calculating Volterra-Hammerstein integral operators with general form dramas for solving problems of analyzing and optimizing nonlinear electrical circuits for measuring and controlling naprometers, modeling, controlling and controlling objects and processes associated with the conversion and transmission of energy, such as energy conversion in various sensors, the passage of signals in the communication lines, is Yeni tepop- and mass transfer, chemical;, and nuclear transformations, etc.

The purpose of the invention is to improve the accuracy of calculations and speed. FIG. 1 shows a block diagram of the proposed device; in fig. 2 is a temporary diagram of the operation of the device blocks.

The device contains a register 1 niara, HcpBbiii block 2 elements And, a first day matrix 3, the first block 4 comparison, the register 5 limit value, the second 6 and the third 7 blocks of elements II, block 8 calculations of the core of the equation, the fourth block 9 elements H, second emitting cjT.ii.jaTop 10, block 11 calculating the integrand function, first multiplying unit 12, second comparing unit 13, second multiplying unit 14, IPI 15 element, HE 16 element, nepBbtfi switch 17, Fifth unit 18 elements And , delay element 19, shift unit 20, second switch 21, sixth unit 22 elements And, a block of 23 elements Ш1Н, the third run-up (its adder 24.

The description of physical processes in solving problems is reduced to solving a Volterra-Hammerstein nonlinear integral equation of the second kind.

y (t) -J k (t, s) (s) ds f (t), (1)

CL

where y (t) is the signal under investigation, k (t;, s) is the core of the integral equation that carries information about the object under study;

F is a given non-linear function;

f (t) is the response of the object to the signal under study; t - time

The efficiency of solving the integral equation (1) depends on how successfully the integral integrator is implemented.

"FC

t) k (t, s) f (f (s) ds (2)

The performance and efficiency of a separate processor and device that implement the integral operator and the Volterra – Hammerstein equation depend on the successful implementation of the integral operator.

The device implements a quadrature method for the numerical implementation of the integral operator (2) by means of the calculated expression I

(ti) h Ajk (tj, t;) F F (tj), (3)

J.O

where is Aj

0.5 at j O, j 1; 1 at O i. j 4 i.

five . five

„

0

five

five

those. the quadrature trapezoid formula with a discretization step h const is realized.

The device works as follows.

Before starting, the step value h is entered into the first register 1, and the upper limit value b of the integral operator is entered into register 5. All other operational blocks are set to O. After the control signal is applied Bus start, the output of the code of the first 3 and second 10 accumulating adders ( The first processor clock cycle) the value t: Ь tp О from the adder 3 is fed to the first input of the first comparison unit 11, the second input of which from the register 5 receives the value b as a result of this, the comparison tg with is executed in the first 4 comparison block. B. At the same time, the value of the variable t t О is fed to the first input of the second comparison unit 13, the second input of which from the accumulating adder 10 receives the value of the variable t tp 0, with the result that at the second comparison unit 13 there is a comparison of the variable tj t with the variable t tg. In addition, at the same time the value of the variable t; It arrives at the p-input element OR 15 (at the output of which, as a result of the execution of a logical operation OR, a zero signal is produced, which performs

control functions) and to the input of block 11 (it calculates the value of the nonlinear function F f (t) J.

In the second cycle, the first multiplier 12 multiplies the step value h from register 1 by the value of the linear function) from block 11. As a result, we get the value of the product h - F (to) j, and the values of the variables tj 0 and t 0 through the open control signal t. b from the first output of the first block 4 comparing the second 6 and third 7 blocks of the elements AND pass to, block 8, as a result of which the core value k (te, to) is calculated. At the same time, the control signal tj tj (ji) is fed to the input of delay element 19, to the reset pin of the third accumulating adder, to the first inputs of the first 17 and second 21 switches and opens the first block 2 of AND elements, with the result that the first accumulating 3 is calculated tt to + h h.

In the third cycle in the first block A, the comparison t j t with b is performed; in the second block 13 of the comparison, tj with t | , in block 11, the value of the nonlinear function F L f (o) is calculated and on the second multiplier 14 the product h k (tp, to) x (to).

In the fourth bar through the open

the control signal tj with tj from the first output of the second comparison unit is a cheated block of 9 elements And the value of h h is fed to the second accumulating adder 10, where the value of tj t tp + hh is calculated, in block 8 the value of the core k is calculated (t, to) in the first multiplier 12 — the product (to); in the shift unit 20, a shift is performed by one bit in the direction of the lower bits of the value of the product hk (t6, to) (t), with the result that the specified value of the product is multiplied by a factor AJ 0.5.

In the fifth cycle, in the first comparison block 4, a comparison of t t with b is performed, in a second block of comparison 13, tj t with t; t-, in block 11, the value (to) l is calculated, in the second multiplier 14, the product of hk (t, t,) (t), and in the third accumulator 24, the value of the function V (to) 0.5 hk (tp , t).

5 5

Q

with

five

. F f (to). After a delay time X, sufficient for fixing and outputting a result, a delay signal arrives from the delay element 19 on the reset bus of the output accumulating adder 24, which clears and prepares it to calculate the next operator value (t).

Thus, the device's work cycle consists of five cycles. Its operation is illustrated by a timing diagram (Fig. 2).

As can be seen from the time digram, paralleling the computational process allows one member of the sum

i.

ZhAj k (ti, tj) (to)

0

five

j o

during t t 5 N.ftt, where N is the number of the sampling node, ut is the time slice determined by the time of information processing in the slowest operating unit of the device. However, after filling all the operational blocks with information about the time spent on the result of calculating one member, the amount due to overlapping work cycles will be T j 2 N, i.e. having installed the device performance will be only about two times less than the performance of its slowest operating unit.

Claims (1)

Invention Formula A device for calculating nonlinear integral operators comprising an element NOT, a step register, a limit value register and a subgroup calculation function block, characterized in that, in order to improve the calculation accuracy and speed, it contains six blocks of AND elements, the control calculation block, a block of OR elements, three accumulating adders, a delay element, two multiplication blocks, an OR element, two comparison blocks, two switches, a shift block, the outputs of the step register being connected to the inputs of the first multiply multiplying the first block and the first inputs of the first block of the AND, which outputs are connected to inputs of the first accumulator sum, Matora which outputs are connected to inputs of the first group of first and WTO of the second block of elements and the outputs of the limit value register are connected to the inputs of the second group of the first block, the sign output. More than which is connected to the second inputs of the second and third blocks of elements, and the sign output Less is with the output of the device CALCULATIONS, outputs the step register is connected to the first inputs of the fourth block of elements I, the outputs of which are connected to the information inputs of the second accumulating adder, the outputs of which are connected to the inputs of the argument the computing unit of the integrand function, the inputs of the second group of the second comparison unit, the inputs of the second group of elements OR, and the first inputs of the third block of elements AND whose outputs are connected to the inputs of the first argument of the control calculation module, the inputs of the second argument of which are connected connected to the inputs of the first multiplier of the second multiplication unit, the outputs of which are connected to the first and sixth blocks of the elements AND, the outputs of the calculation unit of the core of the equation ineny to the inputs of the second factor of the first block five 0 five 0 multiplication, the outputs of which are connected to the inputs of the second multiplier of the second multiplication unit, the first output of the second comparison unit is connected to the first information inputs of the first and second switches and the second input of the fourth block of elements And, the output of the attribute Less than the comparison unit is connected to the reset input of the second accumulating adder , the second input of the first block of elements And, the second information inputs of the first and second switches and the input of the element NO, the output of which is connected to the reset input of the third accumulating The adder, whose outputs are connected to the information inputs of the device, the output of the OR element is connected to the first control switches of the first and second switches and the input of the NOT element, the output of which is connected to the second control inputs of the first and second switches, and the first switch of the first switch. with the second input of the fifth block of elements And, the outputs of which through the shift block are connected to the inputs of the first group of the block of elements OR, the outputs of which are connected to the information inputs of the third accumulating adder, the output to This switch is connected to the second input of the sixth block of elements I.