SU960806A1 - Device for computing polynoms - Google Patents

Description

This is related to digital computing and may be gripenced, for example, in special purpose computing devices for calculating polynomials. A device for calculating polynomials, which is a universal digital computer, is known. The polynomials are calculated in xy by complying with the corresponding; fluent program 111 "However, for a software method of calculating polynomials in a digital computer, it requires multiple multiplication and complexity of operands, multiple access to a memory device, up to:: about the time spent on modifying commands. In addition, the difficulties of obtaining a result of increased accuracy, which causes a slow response of such devices, are difficult. The closest in technical essence to the invention is a mouth containing serially connected smarts (characters associated with a clocking device. This device has a more high speed, since when calculating a polynomial of the form .S x here it does not require multiple referring to a memory device, multiplying and multiplying operands 2. However, the known device also has a low speed, which can be calculated using the formula h - - h - - sdc), 1- (Ph where 1 is bit X and a; and is the degree of the polynomial; t is the summation time, tcd0 is the shift time. In addition, in the known device, the computation process can be started only when all the bits of the operand X are present, which does not allow the computation in time and the bit input of the argument and causes additional time costs if X can enter the device only by a sequential code, for example, when there are restrictions on the number of external outputs when the device is executed in the form of a large integrated circuit, when there are restriction on the bandwidth of the communication channel when the operand X is formed to an analog-digital converter bit-wise equilibration, etc.).

The aim of the invention is to increase speed.

The goal is achieved by the fact that the device containing n multipliers (n is the degree of the polynomial), cy.matop and n coefficient registers, is additionally entered a residual adder, a residual register, a constant register, a digit register, a switch, a coefficient register and N, log, computing blocks, moreover, a-and computing block (i N), in addition to the N-ro block,

- 12, ..

contains multipliers, 2 g squared - r rators, delay element ,. coefficient registers and switches, the information input of the device is connected to the control input of the switch and the inputs of the delay element and quadrant of the first computing unit, the output j-ro of the multiplier (J 1, 2, ..., 2-) i-ro of the computing unit is connected to inputs (2J-1) -th and 2j-ro multipliers and 2j-ro quad (i + l)-ro computing unit, output of the k-ro quad, (k 1, 2, ..., 2) i-ro computing unit is connected to the inputs 2k + l) -ro and 2k-ro multipliers and 2k-ro quad (i + l) -ro computing unit, the output of the 2nd quadrant i-ro computing unit connect with the input of the electronic element, the input of the i-ro quad and multiplier (i + l) -ro computing unit, the output of the delay element i-ro of the computing unit connected to the input of the first multiplier (iil) -ro computing unit, the outputs of all quadrators and the coils are connected to the control inputs of the respective switches, the inputs of which are connected to the outputs of the respective coefficient registers, the outputs of all the switches, the digit register and the residue register are connected to the corresponding residues of the residue adder, the output of which is connected En with the information input of the register of the balance, the control input of which is connected to the clock input of the device and the clock inputs of all multipliers, quadrants and clock input of the register 4 digits, the information input of the Topdtro is connected to the output of the 1атопа, the first and second inputs of which are connected respectively to the outputs of the increment of the residue adder and the constant register, the output of the digit register is the output of the device.

The drawing shows the proposed device.

The device contains an input 1. quadratures 2, 3 delay elements, multipliers 4, switches 5, registers 6

coefficients, adder 7 balance, register 8 balance, adder 9, register 10 constants, register 11 digits, output 12 and clock input 13.

As arithmetic multipliers 4 and quadrants 2, any arithmetic devices can be used, allowing to combine in time the processes of bitwise input of operands and bitwise output of the result

The device works as follows.

In the initial state, in the remainder register 8, in the last registers 6 coefficients of computational blocks and quadrature 2 of the first computational unit are written respectively

., Oh,. .

and r. a,

coefficients p Ej.

The coefficient 6 register at the j-th multiplier of the i-ro block contains the coefficient, - 1, and in the 6 register of the coefficient at the j-th quad of the 1st block, the coefficient is written. + 2 (1 2, 3, 4, ...,

j 1, 2, 3,. . . , 2), where p is the base of the number system, the digits of which take values from the set: IR, -, R., + 1; R, n 2 ,. . ., R2 {; S is the overhead (: as the next digit x () of operand X is on quad 2, multiplier 4, and delay element 3, and r is determined from

r n Bog-pi taflP -.

Ji

The delay S depends on the type of operation and the system used. For example, for the operations of multiplication and erection in kva.drat with; using the p-ary system of numerals with numbers that accept the sign -geni .13 sets

| R ,, 5l2ViMO R2 R2-Ki lP, S, is determined by

s rEog :-p p. ,, i,

where Γ is the function of rounding to a brighter larger integer (cx inin

to “K O, 1, 2, ...).

Similarly, g denotes the number of cycles expressed in U f

bit formation

holding

f-o

relative to the input to the device of the digits X with the same weight. In the register of Constanta, the input is the code of the value G i / P

In each m-th cycle, the computation (m 1, n) at input 1 receives the digit of operand X, having a weight p, which controls the output to cyMi iaTOp 7 of the code X | „a, for example, for binary system Cg: fram l, 0, l}, with a register of 6 coefficients

the adder 7 of the remainder provides an additional code, a for x 1, a direct code a for 1, a code a is not output when x 0. Similarly, the digit of the operand X% having the weight of the first computation unit that forms the output of quadrant 2 controls the output of the code. The variables, a, and operand numbers, having a weight that are formed at the outputs of the j-ro multiplier and the j-th quadrant of the i-ro computing unit, control, respectively, the issuance of codes of the values + +1 and -b. In addition, the adder 7 residue receives the codes of the quantities recorded in the register 8 of the balance and in the register 11 digits. The code generated on the remainder of the adder 7 is fed to the adder 9, where it is summed with the value code (R, / p) coming from the register 10 of the constant. Each ifi-ft calculation cycle ends with a clock signal at a clock input 13, according to which the values- generated on the residual 7 and the adder 9 are written to the residual register 8 and the digit register 11, respectively, and the quadrant of the first group and each j-fi multiplier and the jth quadrant of the i-ro block is prepared for the m + i-My calculation cycle.

The proposed device makes it possible to calculate the value of a polynomial of the nth degree with an accuracy of 1 digit after the decimal point in time T (r 1) (t -t-), therefore, the proposed device surpasses in speed the known K

Ti p-1

X.

TO

In the digital example explaining the operation of the device, S 3, d 4. Thus, the proposed device, for example, when the operand is n 32, allows us to calculate the 3rd degree polynomial 2.6 times, the 7th degree - 6.2 times, 15th degree - D3.3 times faster than the known.

Claims (2)

Invention Formula A device for calculating polynomials, containing n multipliers (n is the degree of the polynomial), an adder l p of the coefficient registers, which is required to add a residual adder, a residual register, a constant register, a digit register, a switch, the register of coefficients and N computational blocks, with the i-th computational block {1 1,2, ... .N), in addition to Y-go.bloya, contains 2 multipliers, quadrants, a delay element, 2 -registers of coefficients and 2 switches, and device information input connected to control switching input and the inputs of the delay element and the quadrant of the first computational 5 blocks, j-ro multiplier output (j 1,2, ..., 2 i-ro computing unit is connected to inputs (25-1) -th and 2j-ro multipliers and 2j-ro quad (i + l) - ro computing unit 0 output of k-ro quad ((2, ..., 2) i-ro computing unit is connected to the inputs (2k + l) -ro and 2k-ro multipliers and 2k-ro quad (i-i-1) computing unit, output The quad of i-ro computing unit is connected to the input of the delay element, the input of the i-ro quad and multiplier (i + 1) -ro of the computing unit, the output of the delay element of the i-ro computing unit is connected to 0 the input of the first multiplier XiO i o of the computing unit, the outputs of all quadrants and multipliers are connected to the control inputs of the respective switches, the inputs of which connected to the outputs of the respective coefficient registers, the outputs of all the switches, the digit register and the residue register are connected to the corresponding inputs of the residue adder, 0 the output of the remainder of which is connected to the information input of the register of the remainder, the control input of which is connected to the clock input of the device and the clock inputs of all multipliers, 5 quadrants and clock input of the digit register, the information input of which is connected to the output of the adder, the first and second inputs of which are connected respectively to the outputs 0 increments of the residual adder and the constant register, the output of the digit register is the output of the device. Sources of information taken into account in the examination 5 1 USSR Author's Certificate No. 170218, cl. G About F 15/20, 1966. 2. USSR author's certificate 451088, cl. G 06 F 15/20, 1974.