SU798862A1 - Device for solving simultaneous linear equations - Google Patents

Description

one

The invention relates to computing and can be applied in the construction of devices for solving systems of linear algebraic equations.

A digital device for solving systems of equations is known, built on the basis of an integrator, including integrators of coefficients, integrators of free members and integrators of unknowns, and the outputs of the integrators of the coefficients of each column are connected to the outputs of the integrators of the free term of the same column / outputs of which are unknown and the inputs of the coefficients integrators of the corresponding lines li.

The disadvantages of this device are a large amount of equipment, low speed, the difficulty of determining the end of the solution.

The closest in technical essence to the proposed. is a device for solving systems of linear algebraic equations, which contains registers of free members, memorization of a block of coefficients, adders, multipliers, registers of unknowns

ema, the outputs of the registers of free members are connected to the first inputs of the first adders of the respective rows of adders, to the second inputs of which the outputs of multiplying blocks are connected, respectively, the adders are connected in series, moreover: the outputs of the last nth adders are connected to the inputs of receiving circuits

0, respectively, whose outputs are connected to the corresponding inputs of the registers of unknowns, whose outputs are connected to a common point of the combined first inputs of the corresponding

5 multiplying blocks of each row of multiplying blocks, the outputs of the storage blocks of coefficients are connected to the common point of the combined second inputs of multiplying blocks

Corresponding dich lines 2.

The operation of the device is as follows. From the outputs, the memorized: the blocks to the inputs of the multiplying blocks of the corresponding lines receive the values of the coefficients by a parallel code, and from the outputs of the registers of the unknown in the corresponding cycle and to the inputs of the corresponding multiplying blocks of each line

Q sequentially (starting with the younger ones)

ranks unknowns. Transmitted bits of the products of coefficients to unknowns in the corresponding cycle are summed up among themselves and with the code of the free term on a sequential adder consisting of n adders. Results of the operations performed

(unpacked code) is transmitted to a receive circuit that converts the received unanswered code to an unknown code.

(for example, a part of the magnitude of the mask is highlighted). The new approximation of the unknown thus obtained will be used in the next iteration. This device has a significant drawback - low power. This is due to the fact that the skew code passes a column of n one-bit adders, and for a sufficiently large order of the solved system of equations, the solution time may be unacceptably long.

The purpose of the invention is to increase the speed of the device.

This goal is achieved by the fact that the device for solving systems of linear equations, containing memory blocks of coefficients, registers of bursts, registers of unknowns, one-bit adders, shift registers, adders and a priority block whose control input is the first the input of each adder is connected to the output of the corresponding storage unit of coefficients, the second input is connected to the output of the corresponding shift register, the input of which is connected to the first output the register house is inverse, the output of each adder is connected to the input of the corresponding register of distractors and to one of the inputs of the priority block, the first output of which is connected to the control inputs of the shift registers, the second output of the priority block is connected to the first inputs of single-bit adders, the control input of each of which is connected to the second output of the corresponding register, the output of each one-bit adder is connected to its second input through the corresponding register of unknowns.

Figure 1 schematically presents the proposed device; figure 2 - scheme of the priority block; on fig.Z - scheme shift register.

The device contains memory blocks of 1 coefficients, adders 2 registers 3 non-current, priority block 4, one-bit adders 5, registers 6 unknowns, shift registers 7, control input 8 of the device, OR 9, shift register 10, And 11 elements, register

12, encoder 1z, triggers 14, elements I 15..

The device works as follows.

In the storage unit 1 of the coefficients, the coefficient codes of the corresponding lines are written in the registers, 6 registers of the unknowns are zero initial approximations of the unknowns, and the registers of the 3 stresses are the codes of the corresponding free members of the solved system of equations. The contents of all adders are set to zero. On, the outputs of block 4 are formed respectively 609-q. K, where K - bit codes 11 ... 1 and 00 ... O (q is the base of the number system).

At zero iteration, the code of the corresponding free member from the register 3 output is through the shift register 7 without delay (a zero signal is applied to its control input) is fed to the input of the adder 2, respectively, to the second input of which nothing is fed. As a result, the codes of the free members pass through the adders 2 without changes, then they go to the registers of slave 3, respectively, and to block 4. In this block, the highest bit of the largest (modulo) free member is selected. The address code of the received high-order bit is set at the first output of block 4, and at the second output - the K-bit code of this high-order bit. The high-order code obtained in this way is the increment value of the unknowns, which varies depending on the signal on the control input 8. The high-order address code controls the delay time using the shift registers 7 for supplying free member codes from the registers 3 in adders 2.

In the first interaction, the storing blocks 1 of the coefficients in adders 2 are successively received bits (starting from the lower ones) of the coefficient codes of the corresponding rows. After a certain number of ticks, determined by the address code of a significant unit of increment of the unknowns, the adders (2) of the lower members of the free members are added to the adders 2. After the above operations, the outputs of the adders 2 produce results representing the codes of the corresponding bins, which go to the corresponding register 3 for storage for the iteration time and to the priority block 4, where the most significant bit is received from the received bins which is the increment value of the unknowns at the next iteration. In the same, first, iteration, simultaneously with the receipt of codes of

TOTAL unknowns approximations. it

The calculation is as follows. and adders 5 receive the codes of the previous value of the corresponding unknown from the registers of 6 unknowns and the increment of the unknown from

Locale 4. The operation mode of adders5 (addition or subtraction) is controlled by codes obtained from the second inputs of the corresponding registers 3 (the outputs of sign bits).

All subsequent iterations are identical to the first.

Priority unit 4 operates as follows. The inputs of the element OR 9 receive bits (starting from the younger ones) of the corresponding nets. The element OR 9 determines the presence of the corresponding value of the unit in the same-bit bits of the codes of all bounds, and the shift register 10 filters this information. The content of the shift register 10 is shifted in each clock cycle one digit to the right (toward the higher bits).

For K clock cycles in the shift register 10, K is received, a bit word, meaning each bit of which indicates its presence in the same bit of even one gap. Next, using elements 11 and identifying the most significant bit of the word stored in the shift register 10. Elements 11 are connected so that the inverse output of each subsequent to the highest bit allows the unit to pass from the direct output, for example, the i-th the bit of the shift register 10 is at the input of the register 12, and all subsequent to the i-th element And 11 remain closed. The allocated code of the higher unit set in register 12 can be changed within the limits of the signal from the control input of register 12 from input 8. The code set in register 12 is the increment code. unknown and fed through the encoder 13 to the first output and without conversions to the second output of block 4. The code received at the second input of the first (FIG. 3) element-I 15 and input

the trigger 14, is delayed depending on the bridge, on the code at the control input of the shift register 7, i.e. at the first inputs of the And 15 elements. For example, with the code on the And 15 101 elements (the old, wide, right, bit is fed to the upper element And 15) the code passed through register 7 ,. delayed by two.

Claims (2)

1. Maiorov FM. Electronic digital integrating machines. M., Mash: Guise, 1962, p.86. I 2. Evreinov E.V. and Prangishvili I.V. {Digital machines with customizable structure. M., Energie, 1974, p. 195, FIG. 6. 7 (prototype). J ".one fi & b