SU1569823A1 - Multiplying device - Google Patents

Abstract

The invention relates to computing and can be used in the construction of specialized processors, in particular, signal processing processors. The purpose of the invention is to increase the speed of the device and simplify it. New in the device containing the multiplier 1, the multiplier register 2 and the adder 4, is the introduction of the multiplier code conversion unit 3 into the canonical sign-digit code, which ensures the minimum possible number of addition operations when performing multiplication. In this case, the multiplication operation can be performed in one somewhat elongated microcommand cycle. The additional hardware costs, compared with the matrix multiplier, which performs the multiplication operation also in one cycle, are about N times less. 1 hp f-ly, 3 ill.

Description

The invention relates to computing and can be used in the construction of specialized processors, in particular, signal processing processors.

The purpose of the invention is to increase the speed of the device and simplify it.

FIG. 1 shows a functional diagram of the device; in fig. 2 - Fragment of the functional scheme of the factor multiplier and the unit for converting the multiplier code into the canonical sign-decoding code | in fig. 3 - a sequence of clock pulses of the device.

The device for multiplying (.fig.1) contains a generator of 1 multiplicand multiplicand, a register 2 multipliers, a block 3 converting a multiplier code into a canonical sign code, an adder 4.

The unit for converting the multiplier code to the canonical sign bit code (FIG. 2) contains (n + 1) multiplier analysis schemes 5, each of which contains the first element AND 6, the first element OR 7, the second, third element AND 8 and 9, the second element OR 10, the fourth - the sixth elements And 11 - 13. Register 2 contains the triggers 14.

The multiple multiplier generator 1 is a tp-bit register for receiving a multiplicand code, connected to (pN) t-cp with key rulers (t-links and in Fig. 1 are shown, m, m and p-multiplicand and multitouch respectively). Coct-niiv -sperms

05

HS

with

shifted relative to each other by one bit to the right. The upper bar serves to shift the multiplicable by one bit to the left relative to the input code, which may be necessary to perform the operation of multiplying by a number greater than 0975. The multiplier generator has m information inputs, device inputs, (monks) outputs, and +1 control inputs (x ;.

In block 3, the multiplier code element AND 6 is designed to form a polling signal for the state of a subsequent bit multiplier.

elements OR 7J,

YU; and elements And 8 {,

11, | intended for analysis and

9;

conversion of bits, multiplier R.J, C; 9 V ;, elements And 12 ;, 13; they are intended to form control signals for the adder Y and the multiple generator of the multiplicand X.

When the subtraction is made from the contents of the adder 4, the number received at its inputs, with addition. When a single value is formed at the output of block 3, which opens the i-th line of keys of generator 1, a code is formed at its output that is shifted to the right by n + 1 -i multiplicand bits.

The device works as follows.

Before the multiplication begins, the multiplicand is placed in the generator of 1 multiples of the multiplicand9 multiplier - in register 2 multiplier, in adder 4 - previous result. With the receipt of the clock signal Ti on the first clock input of the clock signal Ti, the multiplier values are checked (from the lowest to the highest). If the i-th bit of the multiplier is zero, i.e. b, then go to the analysis of b + 1. If b., Then Xj 15 is formed; if this also b, 1, then they form simultaneously with X (and the signal, otherwise (b; H 0; signal .YI 0. At the end of the addition cycle (subtract at)) The multipliers, starting with b and ending with the nearest most significant bit, equal to zero, are transferred to the zero state, and this zero discharge becomes one, for example, the multiplier has a group of three ones, starting with b; (. + on signal and the corresponding partial product will be

0

five

five

0

subtracted from the contents of adder 4, and by signal Tft, bits i, iM, i + 2 multipliers will be set to state O, and bit i + C to state 1. When the next clock signal arrives, the described process repeats . The operation continues until, in all bits of the multiplier, including the additional (n + 1) - and bit (bn +), all units are processed. Consider the order of analyzing and converting multiplier bits and generating control signals X, Y. The signal Z; +1 (Fig. 2) is equal to 1 only in the case when all lower-order multipliers up to (i-t) -ro inclusive are zero. If and b (, then the interrogation signal propagates further in the direction of the higher bits. If, then Z 0 and, thus, the interrogation of the subsequent bits of the multiplier is prohibited by the element And 6,.

Let b,, ..., b, 0, and b; 1, in this case, the signals V, (and Y, are equal to zero, Z 1, Z ,. Element And 12 (by the clock signal Ti forms the signal X; 1, which opens the 1-line generator keys 1. If this and b; f, 15, this element AND 13, simultaneously generates a signal on which a subtraction operation is performed in the adder 4. At the end of a clock cycle (after completion of the addition or subtraction operation in the adder), the Tc signal is set to the O of the trigger 14; register. (multiplier. is set to the zero state R | from the entry of the element AND 8 {. If b, 1, then the signal Y; equal to 1 passes through the element ent GSHI 10, the element OR 72 at the input of the element AND 8 and the signal T

five

0

five

from the output element and 8 trigger

four

t + i

2 multiplier also set- 0,

register 2

is cast into state O. If the group of units in the multiplier code is continued (i.e., ..), ToV, i (1, this ensures that the trigger 14 is suppressed, the multiplier register f и, and so on.

If b

1 + 2.

0, the output signal of the element And 9j sets the trigger 14 ;, register the multiplier to state 1. In this state, the subsequent bits of the multiplier does not change, since the signal V, M will be equal to zero. The values of the signal Z, V, X, Y are set at the very beginning of the summation cycle, therefore with

515698

by obtaining the clock signal Tc, the change in the state of the corresponding bits of the multiplier occurs simultaneously. Thus, the duration of Tc should be sufficient to change the state of one trigger.

Claims (1)

1. A multiplier containing a multiplier register, a multiple multiplier generator, and an adder, the input of the multiplicand device connected to the information input of a multiplier multiplier generator whose output is connected to the information input of the adder whose output is connected to the output of the device whose multiplier input is connected to the information input multiplier register, characterized in that, in order to increase the speed of the device and simplify it, a block for converting the code of the multiplier into a canonical sign is introduced into it code, information bit inputs of which are connected to the outputs of the corresponding bits of the multiplier register, the first and second clock inputs of the device are connected to the first and second clock inputs of the multiplier code conversion module to the canonical sign bit code, the outputs of the first group of which are connected to the corresponding control multiple multiplier generator inputs, installation inputs into O, and the bits of the register of the multiplier register are connected respectively to the outputs of the second and third groups of the code conversion multiplier unit a user in the canonical digit code, the control bit output of which is connected to the control input of the adder. 2, the device according to claim 1, characterized in that the conversion unit of the multiplier code into the canonical sign bit code contains (n + 1) multiplier factor analysis circuits (.n is the multiplier factor), each of which contains six And elements and two the OR element, the first input of the first element AND of the i-th bit analysis circuit of the block multiplier (, ..., n +) is connected to the ith inverse information input of the block, and the output is from 0 five 0 five 0 five 0 five 0 five 23 the input of the first element AND (i + 0th block multiplier analysis circuit, the second input of the first AND element, the first and second inputs of the first element OR the first multiplier analysis circuit of the multiplier of the block are connected to the input of the logical unit of the block, the outputs of the second and third elements And the 1st analysis circuit of the multiplier bits of the block is connected respectively to the i-th outputs of the second and third groups of the block; bit analysis circuits the unit's inhabitant, the output of that element AND the i-th bit analysis circuit, the multiplier of the block is connected to the i-th output of the first group of the block, the output of the sixth cell AND the i-th block analysis circuit of the multiplier of the block is connected to the second input of the first OR element (i + O-th block analysis circuit of the multiplier of the block and i-th control output of the block, the first clock input of which is connected to the first inputs of the second, third and fourth elements AND each i-th block analysis circuit of the multiplier of the block, the second clock input of the block is connected with the first entry of the fifth element AND each i-th analysis of bits of the block multiplier, the second inputs of the fourth and fifth elements AND the i-th block analysis circuit of the multiplier of the block are connected respectively to the (1 + 1) -m and i-th information direct inputs of the block, the first input of the sixth element AND i th analysis of the bits of the block multiplier is connected to (1 + 1.) - the information direct input of the block, the second input of the third element AND the 1st bit analysis circuit of the multiplier of the block is connected to (iH) -M information inverse of the block, in each i-th analysis of the bits of the block multiplier, the output of the first element OR dinene with the third inputs of the third and fourth elements AND and the first input of the second element OR, the second input of which is connected to the second input of the sixth element AND and the output of the fifth element AND, the third input of which is connected to the first input of the first element And, the second input of the second element And connected with the release of the second element OR. SL