SU760085A1 - Binary-decimal-to-binary number converter - Google Patents

Description

The invention relates to the field of automation and computing and can be used when. building code converters * of both regular and mixed fractions, as well as integers.

The known converter of binary decimal numbers to binary, containing the register of the tetrad, the block of storage of binary equivalents, the switch of equivalents and the adder (11-, <.

The disadvantage of this converter is low speed due to the dependence of the speed of its work on the number of binary digits.

. The closest in technical essence and circuit design is a converter ъ binary-decimal numbers to binary, containing; conductive cumulative adder, a register tetrad equivalents switch unit storing binary equivalents shifter and a control unit having an input coupled 'with _m upravlya- guide rail converter, an input switch and equivalents tetrad first input register, a second input coupled to the input bus converter, switch output2

This equivalent is connected to the input of the binary storage unit, equivalent, the output of which is connected to the first input of the shifter, the output of which is connected to the first input of the accumulative adder, the output of which is the output of the converter [2).

The disadvantage of this converter is relatively low speed, since it spends three clocks on processing one binary-decimal digit.

The chain of the invention is to increase the speed by reducing the multiplication time by 10 to two cycles.

<For this, the converter additionally contains the first, second, third and fourth elements, the first, second, third and fourth elements OR, the first and second elements BAN, the output of the first element I is connected to the inverse input of the first element BANNER and the second input of the cumulative adder, the third the input of which is connected to the output of the First BENTER element, the first, second and third inputs of the second element I are connected to the corresponding outputs of the register of the tetrad,

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the first, second and inverse inputs of the third element And are connected to the first, second and third outputs of the tetrad register, the output of the second element And is connected to the first inverse input of the fourth element And, the inverse input of the second element BAN and the first inputs of the first and second elements OR, the third element And connected to the second inverse of the fourth element AND, the first input of the third element OR and the second input of the second element OR, the output of which is connected to the first input of the first element AND, the direct input of the second element REC ET is connected to the third output tetrads register, a fourth output is connected to a second input of said first OR gate, the second, third, fourth and fifth inputs of the control unit are respectively connected to the first output tetrads register output Fourth AND gate, the outputs of the third and first elements · ₂ θ OR, the first, second, third, fourth second control unit outputs are connected to respective inputs of shifter and a fourth OR gate, whose output is connected to the direct input of the first aND gate with inverted, You are a fifth ₂₅

........ the course of the block, the control is connected to the second

the entrance of the first element I.

The control unit contains a pulse generator, the fifth, sixth; seventh and eighth element; And you, the outputs of which are corresponding yuschimi ₃₀ outputs a pulse generator control unit, the input is a first input of control unit, first inputs of fifth / sixth, seventh and eighth elements I'yavlyayutsya second, third, fourth, fifth th block rows ₃₅ vho- control, the first output of the pulse generator is connected to the second inputs of the fifth and sixth elements And is the fifth output of the control unit, and the second output of the pulse generator is connected to the second inputs of the seventh and eighth elements I.,

The drawing shows a block diagram of the converter of binary-decimal numbers to binary / "// '/ th / /. //' 2 '- /// <

The proposed converter contains a switch of 1 equivalents, a block of 2 storage of binary equivalents, a register of 3 tetrads, a shifter 4, a cumulative adder 5, a conversion control block 6 consisting of a generator of 7 pulses and four elements AND 8-11; elements And 12-15, in the third of which one, and in the fourth two inverse inputs; elements OR 16-19, elements BAN 20,

21; the input bus is 22 binary-decimal digits of the number, the control bus 23 and the output bus 24 of the converter.

The principle of operation of the converter is as follows.

The control impulse arriving in each cycle on the bus 23 records the entered binary-decimal digit of the number being converted to the register of 3 tetrads and starts the conversion control unit 6 into operation. The same control pulse for this discharge translates the switch 1 equivalent to read from block 2 of the corresponding equivalent Yu d *. The number of binary equivalents is determined by the decimal digits. The selected binary equivalent is fed by a parallel code to the input of the shifter 4 and is then used as a term in accumulative adder 5, which forms the binary code of a number. The shifter 4 is implemented in the particular case according to the four-input switch 'scheme for each binary digit, on the information inputs of which the corresponding bits of the binary equivalent are applied, which at the output of the signals of block 6 parallel code of the binary equivalent without shifting or shifting the code by one, two or three digits towards the higher digits, which corresponds to multiplying the equivalent by the number two, four or eight / Generator Ί of block 6, when receiving each control pulse, produces two single clock pulses bca, each of which is issued by a private bus and serves as a gate when forming the conversion control signals. The second clock pulse is delayed in time relative to the first. The conversion of each binary-decimal digit is performed by accumulating in the adder 5 the resulting binary code based on the corresponding equivalent according to the result of the analysis of the input tetrad. If at the output of the register 3 tetra ·· d there is a logical unit only in the first (lowest) digit, If the next decimal digit is equal to one, then the second clock pulse from the output of the And 8 element removes the signal allowing the shifter 4 to transmit the information input of the adder 5 of the binary code equivalent without shifting. At the same time, the same signal, passing through elements 19 and 20, allows summation. If there is a logical unit only in the second digit of register 3 (the next binary decimal tetrad equals two) with the help of GZ elements, 14, 15 a signal is generated at the output of the AND 9 element by the second clock pulse allowing the code shift of the equivalent by one digit, the same signal passing elements 19 and 20, forms the resolution of the addition. The presence of a logical unit only in the third digit of register 3 (the decimal digit is four) causes the code shift resolution signal to be generated by elements 21, 18, 10 by the first clock pulse two bits further by element 760085

max 19, 20 resolution addition. The presence of a logical unit only in the fourth (senior) discharge of the tetrad (decimal digit is equal to eight) leads to the formation of elements 16 and 11 on the first clock pulse. _{5 of the} signal, allowing the shift of the code equivalent to three digits, and on the elements 19, 20 the resolution of addition. To convert the code, the remaining input decimal digits are formed on the corresponding elements of the device signals, allowing the execution of operations according to the table:

Input decimal digit Operation 3 4 - 1 five 4 + 1 6 4 + 2 7 81 9 8 + 1

In this case, the signal allowing the subtraction is generated by the second clock pulse on the elements 14, 17, 12 for the number three and on the elements 13, 17, 12 for the number seven. At the same time, the same signal prohibits the formation of the addition signal on the element 20. The signal permitting a shift of two digits For the case of a subtraction operation, is formed on elements 14, 18, 10 by three digits - on elements 13,

16, 11. For the case of the addition operation, the formation of shift resolution signals is performed in a similar way.

Following the first decimal place, in exactly the same way, in one cycle consisting of two before cycles, each subsequent binary-decimal digit of the original number is converted. At the same time, for each new cycle, the next binary equivalent of 10 is read from block 2. This continues ₄₅

until all the binary decimal digits of the source number have been converted, and in the adder 5, the desired binary number is generated, which is read from the output bus 24. to

The proposed converter of binary-decimal numbers to binary implements the FURT process for converting a decimal digit in two cycles. As a result, the conversion time of both regular and mixed fractions, ₅₅ and integers is reduced by 1.5 times.

This increases the noise immunity of the equipment and decreases the possibility of an error in the calculations.

Claims (2)

Claim 1. Converter binary decimal numbers to binary, containing a cumulative adder, register tetrade, switch equivalents, storage unit binary equivalents, shifter and control unit, the input of which is connected to the control bus of the converter, the input of the switch equivalents and the first input of the register of the tetrad, the second input of which connected to the input bus of the converter, the output of the switch of equivalents, connected to the input of the storage unit of binary equivalents, the output of which is connected to the first input from the engine, turn is connected to the first input of the cumulative adder whose output is an output transducer, characterized in that ,, to increase the transformation rate; It contains the first, second, third and fourth elements AND, the first, second, third and fourth elements OR, the first and second elements BAN, the output of the first element AND connected to the inverse of the first element BAN and the second input of the cumulative adder, the third input connected to the output of the first element BANGE, the first, second, and third inputs of the second element And are connected to the corresponding outputs of the register of the tetrad; the first, second and inverse inputs of the third element And are connected to the first, second and third outputs regis the tetrad, the second output element Y is connected to the first inverse of the fourth element AND, the inverse input of the second element BANCH and the first inputs of the first and second OR elements, the output of the third element Y is connected to the second inverse of the Fourth element AND, the first input of the third element OR and the second the input of the second OR element, the output of which is connected to the first input of the first element AND, the direct input of the second element BANGE is connected to the third output of the tetrad register, the fourth output of which is connected to the second input of the first The second element OR, the second, third, fourth and fifth inputs of the control unit are connected respectively to the first register output ί of the tetrad, the output of the fourth element AND, you, by the turns of the third and first element OR, the first, second, third and fourth outputs of the control unit are connected to the corresponding the inputs of the shifter and the fourth element OR, the output of which is connected to the direct input of the first element BAN, the fifth output of the control unit is connected to the second input of the first element I. . 2. Converter π. 1, that is, the fact that in it the control unit contains a pulse generator, the fifth, sixth. the seventh and eighth elements And, the outputs of which are the corresponding outputs of the control unit, the input of the pulse generator is? the first input of the control unit, the first inputs of the fifth, sixth, seventh and eighth elements And are the second, third, fourth and fifth inputs of the control unit, the first the output of the pulse generator is connected to the second-. USSR author's certificate No. 572781, ^! My entrances of the fifth and Shestey elements AND and JAVA-. _<0 cl. C 06 P 5/02, 1976. TSNIIPI USSR State Committee. · Inventions and discoveries. . 113035, Moscow, Zh-35, Raushskaya nab. 4/5 760085 _λ 8 It is the fifth output of the control unit, and the second | the swarm output of the pulse generator is connected to the second, rymi inputs of the seventh and eighth elements I.