SU1662004A1 - Binary coded decimal to binary translator - Google Patents

Abstract

The invention relates to computing and can be used to quickly convert decimal numbers into binary ones. The aim of the invention is to increase speed. The goal is achieved by the fact that in the converter containing input register 1, memory blocks 2, first and second summation blocks 3, 5 and intermediate register 4, the address inputs of memory blocks are connected to the outputs K of the highest tetrads of the tetrad register registers 1, and the outputs summation unit 5 is connected to the inputs of summation unit 3, which provides multiplication by 10 ^K. 2 Il. 2 tab.

Description

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The invention relates to computing and can be used to quickly convert decimal numbers to binary,

The aim of the invention is to increase speed.

Figure 1 shows the structural scheme of the proposed converter of a binary-decimal code into a binary one; Fig. 2 illustrates a 16-bit input code converter with, m 2, p 8, 0 1.

The converter contains input register 1, memory blocks 2, first block 3 of summation, intermediate register A, second block 5 of summation, information input b of the device, control 7 and clock 8 inputs of the converter and output 9.

In blocks 2 of memory, at certain addresses, sums of binary equivalents are stored for the upper tetrads (K 1,2, ...) of the corresponding subgroup of tetrads of the code being converted, into which the register 1 is conventionally divided. Register 1 is divided into m

subgroups (m, where n is the number of bits 8K

input code). A memory unit may combine the outputs of the older tetrads of several subgroups.

The first summation block 3 converts (Q + C) -rd code into S-row, where G is the number of single oases in the binary representation of the weight 10k / 2. The code generated at the inputs of summation block 3 is explained by the fact that the first group of inputs receives m sums of binary equivalents of the upper tetrad subgroups of the corresponding groups stored in memory blocks 2. The inputs of the second group of inputs receive the code formed in block 5 of the summation and shifted by the number of bits corresponding to the numbers of the single units in the binary representation of the weight 10k / 2. For example, if K 1, 101/2 5 101 and the shift is carried out by one and three bits.

The shift is made in the direction of the higher bits (the addition of the shifted code by one and three bits in the direction of the higher bits, is equivalent to multiplying this code by ten).

The second summation block 5 converts the SP code of the code formed at the output of the block 3 of their storage in register 4 into a single-root code. This block can be implemented on high-speed adders with accelerated transfer generation.

The converter works as follows.

Let the binary-decimal code of the number being converted be stored in the initial state in the register 1 of the node, and the register 4 be zeroed. Then in the first cycle of the device

The following action is performed. At the outputs of the memory blocks 2, the values of the sums of binary equivalents of the higher tetrads of the subgroups of the respective groups are formed, which form a Q-bit code that goes further to the first group of inputs of the first summation block 3. The outputs of the second group of inputs of block 3 (with K 1 with a shift by one bit to one input and to the second with a shift to three bits to the side

5 of its most significant bits) receives a one-way code formed in block 5 of summation (in the first cycle its value is zero). Then, using block 3, the summation (Q + 2) -rd code is converted to

0 S-pdny, which is recorded in register 4 by the arrival of the second clock pulse with the resolution of the potential at the input 8 of the device. Simultaneously with writing the information to the register 4, the same clock pulse is shifted by 5 to the decimal places of the register 1. bits This completes the first conversion cycle.

In the second cycle of operation of the device, simultaneously with reading the following binary equivalents from memory blocks 2, the S-code is converted into one-standard by the second summation block 5, the result of this conversion is given

5 to the second group of inputs of the first summation block 3. Upon completion of the transient process in block 3 and upon the arrival of the third clock pulse with the resolution of the potential at input 8 of the device, the conversion result is written into register 4. Simultaneously with writing information to register 4, the contents of register 1 are shifted by K by the same clock pulse by the side of his senior

5 bits

Similarly, all subsequent device operation cycles are performed, the number of which is determined by the number of tetrads in the subgroups of each group of tetrads.

0 Mening the number of tetrads in subgroups, you can thus adjust the speed and hardware costs required to implement the conversion device, which is an advantage of the proposed device.

Example. Conversion of a binary decimal code 1001 1000 0111 0110 (2) 9876 (s) to a binary code. It is assumed that the tetrads of register 1 form one group, which contains two subgroups (m 2),

each of which contains two tetrads. The result at the output of the first summation block 3 is generated in a 2-pd one code (S 2),

The structural diagram of such a device is shown in FIG. Register 1 of the code to be converted indicates the value of the source code. The group of memory blocks 2 in this case can be combined into one memory block with one group of outputs. An example is provided for such an implementation.

The value of bits supplied in the 1st cycle to the address inputs of memory block 2 is given in Table 1.

The process of converting a binary code 1001 1000 0111 0110 to a binary code in the device is shown in Table 2.

Claims (1)

DETAILED DESCRIPTION OF THE INVENTION in m subgroups (m -, where n is the ok width input code, and K is an integer); a group of Q 4 mK / p memory blocks, where p is a number the address inputs of the memory block, the first and second summation blocks and the intermediate register whose information inputs are connected to the outputs of the first summation block, the first group of inputs of which are connected to the outputs of the corresponding memory blocks of the group, the outputs of the second summation block, are information outputs of which are connected to information inputs of the input register, the recording input of which is connected to the control input of the converter and the reset input of the intermediate register, the recording input to Connected to the converter input clock and the input register shift input, characterized in that in order to increase speed, the address inputs of the memory unit of the group are connected to the outputs K of the leading tetrads of the corresponding input register subgroups, the outputs of the second summation unit summation with a shift by R bits towards the higher bits, where R is the number of unit bits in the binary representation of the weight 10k / 2 Table 1 table 2 i9 1 ABOUT I