SU1283978A1 - Binary-coded decimal code-to-binary code converter - Google Patents

Abstract

The invention relates to the field. automation and computer technology and can be used to build converters of whole and fractional decimal numbers into binary ones. The purpose of the invention is to increase the speed of the converter. This goal is achieved due to the fact that the converter that implements the algorithm for summation of equivalents performs simultaneous processing of K decimal places with the formation of a compacted ROM address using an intermediate transducer g for the K bit digit of the binary-ten code in binary code 1 il. //

Description

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The invention relates to computing and can be used to quickly convert both integer and fractional decimal numbers to binary.

The purpose of the invention is to increase the speed of the converter.

The drawing shows the structural scheme of the proposed converter of binary-decimal code to binary. The converter contains an input register 1, a switch of 2 equivalents, the first and second blocks 3 and 4 of storage of equivalents, accumulating adder 5, K-bit converter 6 of binary-decimal code to binary, information information 7 of converter, control input 8 of converter, output 9 converter

The input register 1 is intended to store in binary code the value of the i-th K-bit group of decimal digits of the initial operand for the time period of its conversion (i 1, 2, j- where 1 X is the nearest integer greater than or equal to X; n The bit size of the decimal operand), The binary values of the first and second parts of input register 1 are the minor parts of the addresses where the first 3 and second 4 blocks of binary equivalents are accessed. It is advisable to implement the input register 1 on two-stroke synchronous D-flip-flops.

The 2 equivalent switch selects the high-order part of the binary equivalent addresses stored in blocks 3 and 4. Its bit is determined by the number of K bit groups of decimal digits in the number to be converted. It can be implemented on a push-pull synchronous binary counter.

The first 3 and second 4 blocks are intended for storing binary equivalents of the first and second parts of the double value of the i-th converted 1k-digit group of decimal digits, respectively. The number of binary bits at the output of the first 3 and second 4 blocks of storage of binary equivalents is determined by the number of binary bits contained in the maximum values of binary equivalents. The first 3 and second 4 blocks can be implemented on permanent memory.

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The accumulating adder S produces the summation of binary equivalents selected from the first 3 and second 4 blocks, with the previously accumulated result. It can be constructed on a combinational adder with preserved. Carrying out the carries, leading the three-row code to a two-way, accelerated-transfer combinational adder and a register for storing the result of the summation.

Converter 6 is designed to convert a K-bit group of decimal digits into a binary code. When K 2, it is advisable to implement it on a permanent memory. With K 2, the most acceptable are variants of its construction on combinational circuits.

The basis of the proposed converter of binary-decimal code into binary is the following principle. P-bit conversion

25 decimals occur in

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His decimal pythre is battered, and they are previously converted from a binary-decimal code into a more compact binary code. Since the binary value of the i-th K-bit group of decimal digits can be represented as (A- + B.) - V., where A- and B-, are the first and second parts of the binary value of the i-th group the primary digit is the sum of two binary equivalents of the values A.-V-HB. V. with the sum of previous equivalents.

Consider the work of the proposed Converter when K 3,

Before starting the conversion, the triggers of input register 1, switch 2 equivalents and accumulating adder 5 (these setting circuits are not shown) are set to zero. The converter input receives the binary-decimal value of the first three decimal digits, which is converted by the converter 6 into 10 is a binary code. The first pulse coming from the control input 8 of the converter | writes the binary value of the first three decimal digits into the input register 1, and zero information generated by blocks 3 and 4 on the initial (zero) state of the input register 1 into the accumulator 5 The same impulse switches the switch of 2 equivalents to the formation of the value of the highest part of the addresses of binary equivalents for the cert 3-digit group of decimal digits. The lowest part of the binary equivalent address; the glint of the first term A - V is determined by the value of the first five bits of the input register 1, and the younger part of the binary equivalent address of the second term V V - the value of the second five bits of register 1. The binary equivalents of the first and second terms stored in the first 3 and second 4 storage units of binary equivalents (32 binary equivalents in each block for each 3-bit group of decimal digits, respectively),

The selected binary equivalents are received by a parallel code at the inputs of the accumulator c5T4mator 5, where nx summation is performed.

The second pulse from control input 8 of the converter writes the result of the summation of its initial (zero) content with the value of the first two binary equivalents. The same pulse writes to the input register.

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1 is a binary-converted value of the second three decimal digits and translates a switch of 2 equivalents, to the formation of the value of the highest part of the addresses of binary equivalents for the second 3-bit group. The operation of converter 6 is performed in parallel with the operation of blocks 3, 4 and adder 5.

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Similarly (.), The transformation of each successive 3-digit group of decimal digits comes off until all the decimal digits of the original number are transformed, and the required binary number is generated in the accumulating cyftMaTope 5, which transducer output 9. The total conversion time for an n-bit decimal number is defined by the expression T t, where t is the duration of the execution of one cycle.

Claims (1)

Invention Formula The binary-to-binary code converter, which contains the input register, the equivalent switch, the first and second equivalent storage blocks, and the accumulating adder, whose outputs are outputs. The converter, the control input of which is connected to the synchronous input of the input register of the equivalent switch and accumulating adder, the first and second inputs of which are connected respectively to the outputs of the first and second storage blocks of the equivalent, the lower bits of the address inputs of which are connected respectively to the first and second outputs of the input register, and the high-order bits of the address. inputs of the first and second equivalent storage units are connected to the output of the equivalent switch, which is Accelerating operating speed of the transducer, it is entered K-bit converter binary coded decimal to a binary code, to torogo output connected to the input of the input register and input - with an information input transducer. "five 7V A tea / h / h