SU723583A1 - Arrangement for computing sine and cosine functions - Google Patents

Description

The invention relates to the field of computer technology and can be used in devices for the pre-installation of a parallel angle code into sine and cosine codes. A device for calculating a sine and cosine function based on tables stored in a permanent memory unit (ROM) 1 is known. However, the use of GOUs, providing more rapid response, requires a large amount of memory to obtain high accuracy of calculations. The closest in technical terms to the proposed is a device for calculating sine and coc sine functions, containing an n-bit input register, an adder submodule two, the first and second switches, a reversible counter, a memory unit, a number-pulse converter, a control unit clock generator, the forward and inverse outputs of the lower bits of the input register (from first to nth) through the first switch are connected to the corresponding inputs of the first group of number-pulse converter, inverse the outputs of the bits of the input register {s (t + 1) -th to (n-2) -yo1. are connected to the corresponding inputs of the second switch. The outputs (n-l) -ro and the nth bits of the input register are connected to the inputs of the modulo-two adder. The output of the modulo two adder and the output of the Nth bit of the input register are respectively the output of the cosine sign and the output of the sine sign of the device. The first group of outputs of the memory unit is connected to the setup inputs of the reversible counter, the bit outputs of which are the information outputs of the device. The output of the generator is connected to the clock pulse, and the output (m -1) of the input register and the overflow output of the number-pulse converter are connected to the corresponding control inputs of the control unit, the outputs of which are connected respectively to the control input of the second switch, clock and setup inputs of a pulse-pulse converter and a recording control input of a reversible counter. One of the outputs of the control unit is the output of the sine function termination shaping function, and the other is the output of the sine function generation shaping signal of the device 2. However, this device has a low computation accuracy and low speed. The circuit of the invention is to improve the accuracy and speed of the device for calculating the sine and cosine functions. This is achieved by the fact that the device for calculating the sine and cosine functions contains an address adder, a correction adder, a NOT element, three AND elements, an OR element, and the low-rank output of the second switch is connected to the input of the first, and the other outputs of the second switch the summation of the address adder, the outputs of the digits of the sum. Which are connected to the address inputs of the memory unit, and the output of the overflow to the nepBoi% iy input of the first and through the element NOT to the first input of the second and first input of the third I. o, the second and third elements And through the element IL are connected to the counting input of the reversible counter. The inputs of the first and second components of the correction adder are connected, respectively, to the second and third groups of outputs of the memory block, the control input of the correction adder is connected to the output i / second bit of the second switch n to the control input of the reversible counter, the outputs of the counter accumulator of the second switch, a group of inputs of a pulse-frequency converter. The second input of the first segment I is connected to the control input of the record of the reversible counter, the second input of the second element I is connected to the pulse-output number-pulse converter. The second input of the third element I is connected to the output of the high bit of the correction adder, the third and fourth inputs of the third element I, respectively, to the direct output of the () th bit of the input register and the overflow output of the number-pulse converter. The inverse output (W + 1 th bit of the input register is connected to the stinging input of the first switch on the input of the first bit of the first 7 34 group of inputs of the pulse-pulse converter. Functional, the device circuit for the case m 5.1 l 12 is shown in the drawing. Device contains input register 1, modulo two 2, first 3 and second 4 switches, reversible counter 5, generator 6 of sinusoidal approximation code consisting of address adder 7, memory block 8 in the form of permanent memory (ROM), adder to 9, number-pulse converter (CHIP) 10, NOT 11 element, AND 1214 element, OR 15 element, control unit 16, clock generator 17, output (nl) -ro of bit 18, control input of the second switch 19, the output of the lower 20 bits of the second switch, the output 21 of the address adder overflow, the setup input 22 of the pulse converter, the number of pulses of the output 23 of the pulse converter, the output of the senior bit of the correction adder, direct output 25 (t + 1) - th bit input register output 26 overflow number pulse a multi-converter, a clock input 27 of the number-pulse converter. The device works as follows. In the device, a 12 - bit angle code, cf, the Oyos6.27t: (), register 1 is synthesized in each conversion cycle 11 - bit codes. and sov CV. and also forms the pulse of the end of the code definition cos and the pulse of the end of the code definition eip and outputs this information to the outputs. The leading bits of the codes sin and coSc are sign and are determined by the two most significant bits of register 1. Therefore, the 12th bit of register 1 is the sign bit of code sifi l. , and the sign bit of the COS J code is determined by adder 2 as the sum modulo two logical values of the 11th and 12th bits of register 1. The codes of numbers and | coB (A. | are determined by the piecewise-slice approximation method and using The approximation of the functions is performed by the sinus function at the corner (. (-f-r-) which is divided into 17 equal sections. The magnitude of each of. ".r. of these sections is equal to radians, and the node point is selected in the middle of the section of approximation Using the control unit 16 codes l indlf and Icob- t defined are successively in each conversion cycle consisting of two periods T1 and T2. During T1, the code | sii is determined (l and during T2, the code | coscC | Therefore, the control unit 16 is based on the value of the 11th angle of the register angle 1, at output 19, produces for the code switch 4 a control signal in the same way that during T1 the 5-bit code of the angle (Tl) tx: ,,. Aliv5c np.v.control a is removed from the outputs of the code switch 4; T2-5-bit bottom angle code. ) -oc ,,,. QM where O-11-bit 5: 1st is the coefficient of the 11th bit 1, and (.- is an angle whose value is defined by the register bits, 1 from the 6th digit to the 10th The bit that represents the control part of the angle from register 1, according to which the definition of the starting point of the approximation section and the direction of change of the function during the approximation (from left to right or from right to left of the starting point of approximation) The lower five bits of register 1 define the angle "appr., Which is appr The immersing part of the corner register 1, which is used for the final definition of the function (for T1 and 1CC, 1 for T2. The forward and inverse code of the angle i is appr. from the outputs of register 1 goes to the switch 3, the operation of which is controlled by 6-bit of register 1 in such a way that at the outputs of the switch of codes 3 a five-bit code of the angle is generated, .c "b - - oppr / Code 3 appr. Cb enters the Hbie inputs of the higher bits of the chip 10, per low-end information input CHIP 10, in order to increase the conversion accuracy la ASDP. (cb) the pulse number code comes from register 1 inverse value of the 6th digit of the angle 5.. designating the code gsh informational inputs 10 through:. appr. (cb) appr (ab) annpiC Voc pe where c. appr. - is a 6-bit angle code (the low-order weight of this code is equal to radians), the lower-order bits of which are always O, and the higher bits are determined by the angle code. Before the start of the conversion cycle, the counter 5 and CHIP 10 contain the previous conversion cycle, i.e. In counter 5, the coj code A. is stored — the previous conversion cycle, and CHIP 10 is in O. From the code 4 switch outputs, the code of the 4 most significant bits of the CTC angle (T1) and, from the .20 output, the low code value . (T1) are received respectively at the inputs of the first term and the input of the second one-bit term adder of address 7. Code o. ex. (T1) adder address 7 performs 4-times. the common code of the sum j (T1) and the logical signal of the overflow sign P21, generated at the output 21 of the address adder 7. The code (T1) is defined by the expression (tO |%, 2 of the number of OD .... 14.15, where responsibly the bit and weight coefficients are the first bits of the code j (T1). adder 9, In this case, if A is 0, then the counter - 5 is set to the account in +, and if A 1, then the account is allowed in - In addition, depending on the value of D n At the outputs of the adder 9, a six-digit code of the angular coefficient is generated on the right or left half of the approximation segment, i.e. the code Krn). TL) (t CHIP 10 arriving at the numeric inputs. The logic signal from output 21 directly controls the operation of element I 12 through the first input, and through the element 11 not 11, through the first inputs - operation of elements 13 to 14. Let the conversion cycle considered correspond to code of angle 2, which is during T1 and T2. The cycle starts with an input from the source 7 .7

control 17 on the control unit 16

start-up pulse. By the start-up pulse, the control unit 16 at the output 22 generates pulses of the beginning of the period, which is used to write to the counter 5 of the code (T2) -dcx; And in the chip 10 code

 W ® Opp.-V.

After that, the control unit 16, based on the number of pulses from the sync pulse 17 and output 27, generates a series of (N + 1) pulses per clock input of the CHIP 10. The S4 pulses of this series are the numbered pulse code of the pcppr angle. (Ol6) Chuck oSappr. (ab) j according to which CHIP 10 at output 23 produces, the number of pulse code is

 OpprHae). (To j.vA Ki (,,)

each pulse of which has a weight of 2 and enters (since) through elements 13 and 15 to the counting input of the counter-register 5. As with (code, ch4appr (ob) Sapp. then by force) - A.К j () VA (to j (C, from the output 26 of the CHIP 10, the overflow pulse also enters the feedback input of the control unit 16. After the end of this pulse, the controlling unit 16 inverts the control sigal at i output 19 in such a way that from the outputs of switch i of codes 4 the code of the angle ctynpiTZ) -c pQ "V; jTa will be removed and forms the pulse of the end of the period T1, according to which the converter outputs are removed to slaoc After this- .. -...).. Av (-A) .2- ° .a6.K6. After the end of the (N + 1) CHIP pulse, 10 is set to O. After that, the control circuit generates a pulse g by which the output of the converter can be removed by the code. The calculation cycle ends and the next cycle starts only when the control unit 16 arrives from source clock 17 of the next start-up pulse. In the case when in one of the conversion periods a tfiznak of overflow of the adder of address 7 is generated, i.e. when 021-1, based on the pulse of the beginning of the conversion period, is produced at the output 22 of the control circuit 16, the chip 10 and the counter-register 5 are recorded corresponding to

35838

Binary reverse code information specification specifications CHIP ° app. will be presented with an error of one quantum. Therefore, the impulse repetition pulse 5 CHIP 10 (the impulse overflow generated by chip CHIP 10 by (N +1) impulse at its clock input, on which the output pulse at output 23 CHIP 10 is not generated, which is a feature of chip 10) is used to correct this error . At the output of the element is And 14 at, and. (K6-bit coefficient of the code of the most significant bit of the corrective

 adder 9) on the pulse of overflow of the CHIP 10, coming from the output 26 of the CHIP 10 to the fourth input of the element I-14, produces a pulse pulse, which enters through the element 15 to the counting input of the counter 5, Therefore, after entering the clock input of the CHIP 10 (N + 1) pulses at the outputs of the counter-register 5 when the number code is generated

Claims (2)

1. Author's USSR Embassy No 510717, cl. G 06 F 15/34, 1974. 2. Author's testimony of the USSR K 362448, cl. G 01 S 7/12, 1970 {prototype). Cos sign } fod jSfnef / unt / Cofef / h