SU1035600A1 - Multiplication device - Google Patents

Abstract

A DEVICE FOR MULTIPLICATION, containing registers of multiplicable, multiplier and product, matrix of multiplication blocks and summing block, with the first inputs of multiplication blocks of each row of the matrix connected to the outputs: the corresponding tetrads of the multiplicative register of the matrix column multiplied with the outputs of the corresponding matrix. the multiplier register's tetrad, the outputs of the summing block are connected to the inputs of the product register, characterized in that, in order to reduce the number of equipment when multiplying two but coded decimal numbers summation. the root block contains binary sum tori, converters of binary code into a binary-decimal and binary-decimal adder, and the inputs of the K-th binary adder (K. 1, .., m + No.-3; M is the number of decimal digits multiplicates. And - the number of decimal digits of the multiplier is connected to the outputs of the i-th blocks of the multiplication of the j-th rows of the matrix (... N; J 1, ..., / Л; 1+ j.lt- 2). The outputs of the first multiplication block of the first matrix, binary adders from the first to (M + M-3) -th and N-ro blocks to multiply the matrix row are connected to the inputs of the binary code converters to the binary-decimal of the first ito (H + LL-1), respectively, the output of the binary-to-binary converter § (p, .. ,,; 6 is the number of outputs of the given i binary-converter in the DVO-1 / L-decimal , (, ..., N + AL-1) is 1, one-in-one with (p + s), -2) -th bit of the PS, and the binary-decimal adder, I the first output of the first, the converter H of the binary the binary-decimal code and the bits of the binary-decimal adder are outputs of the sum block. sl 3t

Description

The invention relates to computing technology and is intended for use in universal and specialized digital computers.

A device for multiplying binary-decimal numbers is known, which contains matrix multiplicators for performing binary multiplications of decimal digits and a device for converting. wands of seven-bit binary products into two-bit binary-decimal products fl}.

The disadvantage of this device is the sequential and multiplier | to work, in which the multiplicand is. therefore, it is multiplied by the decimal places of the multiplier, and subsequently, its speed is small.

The closest. is a multiplication device containing registers of multiplicable, multiplier and product, a multiplication block matrix and a summation; the block, the first inputs of the multiplication blocks of each row of the matrix are connected to the outputs of the corresponding rpimn register multiplicative, the second inputs of the smart blocks .t of each column of the matrix are connected to the outputs of the corresponding multiplier register, the outputs of the summing block are connected to the inputs of the product register, output i th block is clever, - the js of the j –th row of the matrix (i 1, ..., / W;, ..., M; M is the number of groups of multiplicates of M, the number of groups of bits of the multiplier) are connected to the inputs (1 + -1) -th and (1 + J) -and groups of discharge - (Dov summing block while the blocks are multiply and it is in the form of nodes nonvolatile memory 2.

A disadvantage of this device is that when multiplying binary-decimal numbers significantly, it is difficult to execute multiplication blocks, which must multiply single-digit decimal numbers specified in binary code. At the same time, in particular, the Ps1m volume of the nodes used is increasing.

 The aim of the invention is to reduce the amount of equipment when multiplying binary-decimal numbers.

To achieve this goal, the multiplier contains the multiplicative, multiplier and product registers, the multiplication block matrix and the summing block, the first inputs of the multiplication blocks of each row of the matrix are connected to the outputs of the corresponding tetrads of the multiply register, the second inputs of the multiplying blocks of each column of the matrix are connected to the outputs, corresponding tetrads of the multiplier register, output - summing block are connected to the input. tistra of the product; - holds binary adders, converters of binary code into binary-decimal and binary dec; The primary adder, the input of the K-th binary adder (, ..., N + M-3; N is the number of decimal digits of the multiplicand, M is the number of decimal digits of the multipliers) connected to the outputs of the i-th multiplication blocks j - X matrix constructions (, ..., N; j 1, ... M; 1 +; (K -2, outputs of the first block multiplying the first matrix setting, BINARY adders, from the first to (+ M-3) -th and of the m-th block of multiplication of the M-th row of the matrix are connected to the inputs of the binary code converters to the binary-decimal from the first to (N + M-1) and, respectively, the p-th output of the -th converter of the binary code to the binary-decimal (R ,...; E is the number of outputs of this binary-to-binary converter; C) l, v .., K + M-1) is connected to the input (p + d, “2) -th bit of the binary-ten adder, disconnect the output of the first binary-to-binary converter and the outputs of the bits of the binary-decimal adder are the outputs of the summing block.

The drawing shows a functional diagram of a multiplier for the case of multiplying two three-bit decimal numbers.

The device contains 1 three-bit multiplicative register 1, three-bit multiplier register 2, six-bit multiplication register 3, nine multiplication blocks 4, summation block 5, which included binary susceptibility indicators 6, binary-to-binary converters 7 and binary-decimal adder 8. Blocks 4 have outputs 9-17, converters 7 have outputs 18-22, adder 8 has outputs 23-28. Multiplication blocks 4 may be combinational or made in the form of nodes of a permanent memory. Converters 7 are made of combinational.

The operation of the device "-can be shown by the example of multiplying two-three-digit decimal numbers

.

A A, A X a. B, B 0. 1 O and 1 o

In the first multiplication step, multiplication blocks 4, which perform binary multiplication, are multiplied. among themselves the decimal digits of the multiplicand and the multiplier coming from registers 1 and 2. The first step in this example consists of nine multiplication blocks 4, on which nine partial semi-digits of binary products are formed

 ARB,, A,,,, A, VA, A2.V2. In the second stage, in three bits, partial products of the same weight on adders 6 are rolled into single-phase binary forms V; In the third step of multiplication, the single-serial binary forms of the sum of the partial T1 products in the five converters 7 are converted into the binary-decimal form. Due to the increase in the number of partial products in three medium converters 7, the number of decimal digits at the output is increased to three. Neighboring binary-decimal partial products are obtained with an overlap of at least one decimal place. On the fourth the multiply steps of the sum of partial products in binary-decimal form with overlaps on a multi-bit binary-decimal adder 8 are collapsed into a final binary-decimal product, which is stored in the register, product 3. Let er, multiply two three-digit numbers:; 621х 325 201825 А „1 Вл 5 В 3" а о а - в „6" 1 shows the values of partial products resulting from multiplying the decimal digits of the factors on smart blocks 4.m - ....-, Table Outputs 10 11 12 13 14 15 16 17 blocks 4 9 Binary values 05 02 10 03. 04 30 06 12 18 As a result of the addition of partial products of equal weight, binary values of 12, 37 are formed on the binary summators 6, 18, thus the binary values 05, 12, 37,18,18 are received at the input of the converters 7, respectively. The values of partial products are shown as a result of their conversion to binary-decimal form on converters 7 Table2 Transmitter outputs 7 18 19 20 21 22 Values (binary) 05 012 037 018 18 Table. 3 shows the final values of the binary-decimal digits of the product as a result of the addition on the binary-decimal adder 8 Table 3 Outputs the sum 23 24 25 26 27 of the torus 8 Values (binary-decimal) The effectiveness of the invention lies in the fact that more than simple binary blocks and multiply, this will reduce the amount of used OBO1 Satisfaction, in particular, when executing these blocks on the nodes of the fixed memory, the memory size is conserved.

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Claims (1)

A device for multiplication, containing the registers of the multiplier, multiplier and product, a matrix of multiplication blocks and a summing block, the first inputs of the multiplication blocks of each row of the matrix being connected to the outputs of the corresponding tetrads of the register of the multiplier, the second inputs of the multiplying blocks of each column of the matrix being connected to the outputs of the corresponding multiplier register tetra , the outputs of the summing unit are connected to the inputs of the product register, characterized in that, in order to reduce the amount of equipment when multiplying binary-ten number of numbers, sum. The block contains binary sums: tori, converters of the binary code to binary decimal and binary decimal adder, the inputs of the Kth binary adder (K. = l, ... .N + M- 3; M is the number of decimal places, many *, and I is the number of decimal places of the factor) are connected to the outputs of the i-th blocks of multiplication of the J-th rows of the matrix (i®l, = 1, ..., DM i +) =. 19- 2), the outputs of the first block of multiplication of the first matrix, binary adders from the first to the (N + M-3) th and N-ro block of multiplication of the Mth row of the matrix are connected to the inputs of the binary to decimal converters from the first By (M + LA-1) th, respectively, ^{and the} p th output transducer ty-ro Nogo binary code in BCD (p = 1, ..., 6; p-number of outputs' of the binary code converter in the binary de decimal, ty »l, ..., Ν + ΛΛ-1) is connected to the input of the (p + q, -2) -th digit of the binary-decimal adder, the first output of the first binary-to-decimal binary converter? and binary output decimal ·! th adder are the outputs of the summing block.