RU2022340C1 - Vector modulus computer - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has three comparison units 1,3,4, switch 2, AND gate 5, three multirange code converters 6,7,8, three AND gate units 9,10,11, and adder 12, all functionally interconnected. EFFECT: improved speed of response. 2 cl, 5 dwg, 1 tbl

Description

 The invention relates to computer technology and can be used in high-speed specialized calculators.

, со- держащее два коммутатора, три блока сравнения, элемент И, два умножителя, шесть блоков задания коэффициента и сумматор, причем входы первого и второго аргументов устройства соединены соответственно с первым и вторым информационными входами первого коммутатора и первым и вторым входами первого блока сравнения, прямой выход которого соединен с управляющим входом первого коммутатора, выход которого соединен с первыми входами второго и третьего блока сравнения, соответственно прямой и инверсный выходы которых соединены с первым и вторым входами элемента И, первый и второй информационные и управляющие входы второго коммутатора соединены соответственно с входами первого и второго аргументов устройства и инверсным выходом первого блока сравнения, выход второго коммутатора соединен с вторыми входами второго и третьего блоков сравнения и первым входом первого умножителя, выход которого соединен с первым входом сумматора, второй вход которого соединен с выходом второго умножителя, первый вход которого соединен с выходом первого коммутатора, инверсный выход второго блока сравнения соединен с входами первого и второго блоков задания коэффициента, выход элемента И соединен с входами третьего и четвертого блоков задания коэффициента, прямой выход третьего блока сравнения соединен с входами пятого и шестого блоков задания коэффициента, выходы первого, третьего и пятого блоков задания коэффициента соединены с вторым входом второго умножителя, выходы второго, четвертого и шестого блоков задания коэффициента соединены с вторым входом первого умножителя.The closest in technical essence to the proposed is a device for calculating the function Z =

comprising two switches, three comparison blocks, an AND element, two multipliers, six coefficient setting blocks and an adder, the inputs of the first and second arguments of the device being connected respectively to the first and second information inputs of the first switch and the first and second inputs of the first comparison block, the direct output of which is connected to the control input of the first switch, the output of which is connected to the first inputs of the second and third comparison units, respectively, the direct and inverse outputs of which are connected to the first and second the input inputs of the element And, the first and second information and control inputs of the second switch are connected respectively to the inputs of the first and second arguments of the device and the inverse output of the first comparison unit, the output of the second switch is connected to the second inputs of the second and third comparison units and the first input of the first multiplier, the output of which connected to the first input of the adder, the second input of which is connected to the output of the second multiplier, the first input of which is connected to the output of the first switch, the inverse output of the second As the comparison is connected to the inputs of the first and second coefficient setting blocks, the output of the And element is connected to the inputs of the third and fourth coefficient setting blocks, the direct output of the third comparison block is connected to the inputs of the fifth and sixth coefficient setting blocks, the outputs of the first, third and fifth coefficient setting blocks are connected with the second input of the second multiplier, the outputs of the second, fourth and sixth blocks of the coefficient are connected to the second input of the first multiplier.

 The disadvantage of this device is the low speed.

 The purpose of the invention is improving performance.

 The goal is achieved by the fact that in the device for calculating the vector module containing the first, second and third comparison blocks, a switch, an adder and an element And, the inputs of the first and second arguments of the device are connected respectively to the first and second information inputs of the first comparison block and switch the inputs of which are connected respectively to the first and second outputs of the first comparison unit, the first output of the switch is connected to the first information inputs of the second and third comparison units, the second output the switch is connected to the second information inputs of the second and third comparison units with a shift of one and two bits respectively towards the higher digits, the second output of the second comparison unit and the first output of the third comparison unit are connected to the first and second inputs of the element And, the output of the adder is the output of the device , the first, second, and third converters of a multi-row code into two-row and the first, second, and third blocks of AND elements are introduced, each of which contains two groups of AND elements, the first inputs of which are respectively, the first and second information inputs of the block of elements And, the control input of which is connected to the second inputs of the elements And of both groups, the outputs of which are respectively the first and second outputs of the block of elements And, and the first output of the switch is connected to the first inputs of the first, second and third converters of multi-row code in two-row, the second inputs of which are connected to the second output of the switch, and the first and second outputs of the first, second and third converters of a multi-row code into a two-row connection are connected respectively with the first and second information inputs of the first, second and third blocks of elements AND, the first outputs of which are connected to the first input of the adder, the second input of which is connected to the second outputs of the first, second and third blocks of elements AND, the control input of the first block of elements AND is connected to the first output of the second block of comparison, the control input of the second block of elements And is connected to the output of the element And, and the control input of the third block of elements And is connected to the second output of the third block of comparison.

 In FIG. 1 presents a structural diagram of the proposed device; in FIG. 2 is a block diagram of a multi-row to two-row code converter; FIG. 3 ... 5 illustrates the process of transforming code matrices z.

 The device (Fig. 1) contains a first comparison unit 1, a switch 2, a second 3 and a third 4 comparison blocks, an And 5 element, a first 6, a second 7 and a third 8 multi-row code converters, the first 9, the second 10 and the third 11 blocks of AND elements , adder 12, inputs of the first 13 and second 14 arguments, output 15.

 The multi-row code converter (Fig. 2) contains α layers of 16 adders (α is the number of clock cycles of the original code matrix z to a two-row result code) containing blocks of 17 adders of the same weight, consisting of one-bit three-input adders 18.

Устройство функционирует под воздействием синхронизирующих сигналов, подаваемых на коммутатор (на фигурах не показаны).The device implements the same approximating dependence as the prototype:

The device operates under the influence of synchronizing signals supplied to the switch (not shown in the figures).

х

и

y

. Коммутатор 2 реализует операцию по первому (А) и второму (В) выходам:

$\genfrac{}{}{0ex}{}{\text{B=y,}}{\text{B=x,}}$ $\genfrac{}{}{0ex}{}{\text{если}}{\text{если}}$ $\genfrac{}{}{0ex}{}{\text{x≥}}{\text{x<}}$ _y ^y
В результате сравнения на втором выходе блока 1 образуется сигнал единичного уровня в случае, если

х

<

y

. Этот сигнал вызывает появление аргумента

y

на первом выходе коммутатора 2, а аргумента

х

на втором выходе коммутатора 2. В случае

х

≥

y

сигнал единичного уровня образуется на первом выходе блока 1. По этому сигналу на первом выходе коммутатора появляется аргумент

х

, а на втором -

y

.On buses 13, 14, direct codes are received at the inputs of switch 2 and block 1

x

and

y

. Switch 2 implements the operation on the first (A) and second (B) outputs:

$\genfrac{}{}{0ex}{}{\text{B = y}}{\text{B = x}}$ $\genfrac{}{}{0ex}{}{\text{if}}{\text{if}}$ $\genfrac{}{}{0ex}{}{\text{x≥}}{\text{x <}}$ _y ^y
As a result of the comparison, a unit level signal is formed at the second output of block 1 if

x

<

y

. This signal causes an argument to appear.

y

on the first output of switch 2, and the argument

x

at the second output of switch 2. In the case of

x

≥

y

a unit-level signal is generated at the first output of block 1. According to this signal, the argument appears on the first output of the switch

x

and on the second -

y

.

 Blocks 3 and 4 work similarly to block 1, producing results of comparison of the values of A and 4B, A and 2B, respectively. The signal from the first output of block 3 (A ≥ 4B) is the control for block 9 of AND elements, the signal from the second output of block 4 (A <2B) is control for block 11, the combination of signals from the second output of block 3 and the first output of block 4 on the element And 5 (4V> A ≥ 2V) provides a control signal for block 10.

Blocks of elements And 9, 10, 11 provide the passage to the outputs of the adder 12 of one of the three conversion results in the converters 6, 7, 8 - respectively, two-line code matrices z ₁ = 0.996A + 0.122V, z ₂ = 0.941A + 0.347V, z ₃ = 0.817A + 0.588V. Paraphase codes A and B are received at the inputs of converters of a multi-row code. The converters are based on the principle of replacing operations of multiplying arguments by m-bit constants with operations of adding arguments shifted by the number of bits determined by the position of units in the binary constant code (table for m = 8) .

The code matrix (CM) thus obtained contains the number of terms, determined by the number of significant units, in the constants k ₁ and k _{2 of the} approximation. If the number of significant units in the code is more than half of the digits, then it is advisable to switch to the representation of the constant in the form k = 1-k _extra , where k _extra is the additional code of the original constant. This allows you to reduce the calculation time. Obviously, this approach is applicable to the approximation of z ₁ .

/256), прямой код аргумента В, обратные коды аргумента В, сдвинутые вправо соответственно на один, два и три разряда (

/2 +

/4 +

/8 ≈ 0,878

). Точками на фигуре обозначены двоичные разряды кодов соответствующего веса, кружками - разряды, принимающие значение старшего разряда обратного кода, знаком "+" - код коррекции (КК), служащий для образования дополнительного кода из обратного - единица младшего разряда обратного кода. Рамки окружают разряды, подаваемые на входы сумматоров. Номера тактов преобразования представлены возле горизонтальной линии, там же в скобках указано время преобразования в тактах работы одноразрядного сумматора. Фигура показывает, что младшими разрядами КМ можно пренебречь.In FIG. Figure 3 shows the process of transforming the code matrix z ₁ formed by switching data lines of the corresponding weight of the inputs of the converter with the inputs of its adders: direct code of argument A, reverse code of argument A, shifted to the right by seven digits (

/ 256), the direct code of argument B, the reverse codes of argument B, shifted to the right by one, two and three digits (

/ 2 +

/ 4 +

/ 8 ≈ 0.878

) The dots on the figure indicate the binary digits of codes of the corresponding weight, the circles indicate the digits that take the value of the highest digit of the reverse code, the “+” sign indicates the correction code (QC), which serves to form an additional code from the reverse digit — the unit of the least significant digit of the reverse code. Frames surround the bits supplied to the inputs of the adders. The numbers of the conversion clocks are presented near the horizontal line, in the same place in brackets the conversion time is shown in the clock cycles of the single-digit adder. The figure shows that the lower bits of the CM can be neglected.

In FIG. 4, 5 shows the process of converting KM z ₂ and z ₃ . Designations are the same as above.

The last step of the conversion to a single-line result code in all three cases is performed on the parallel adder 12. Its capacity is determined by the capacity of the largest of the two-line CM z ₁ , z ₂ , z ₃ . The capacity of the adder 12 may be equal to the capacity of the arguments, then the lower bits of the CM can be truncated as not affecting the accuracy of the result. At m≥7, the error due to truncation does not exceed the maximum approximation error.

Claims (2)

 1. A DEVICE FOR CALCULATING A VECTOR MODULE, comprising first, second, and third comparison blocks, a switch, an adder, and an I element, the inputs of the first and second arguments of the device being connected respectively to the first and second information inputs of the first comparison block and switch, the control inputs of which are connected respectively with the first and second outputs of the first comparison unit, the first output of the switch is connected to the first information inputs of the second and third comparison units, the second output is with the second information and the inputs of the second and third comparison blocks with a shift of one and two bits towards the higher bits, the second output of the second comparison block and the first output of the first comparison block are connected to the first and second inputs of the element And, the output of the adder is the output of the device, characterized in that the first, second, and third converters of a multi-row code into two-row and the first, second, and third blocks of AND elements, each of which contains two groups of AND elements, whose first inputs are respectively the first and second information inputs of the block of elements And, the control input of which is connected to the second inputs of the elements And of both groups, the outputs of which are respectively the first and second outputs of the block of elements And, the first output of the switch connected to the first inputs of the first, second and third converters of multi-row code in two-row, the second inputs of which are connected to the second output of the switch, and the first and second outputs of the first, second and third converters of the multi-row code into two-row are connected respectively with the first and second information inputs of the first, second and third blocks of elements And, the first outputs of which are connected to the first input of the adder, the second input of which is connected to the second outputs of the first, second and third blocks of elements And, the control input of the first block of elements And is connected to the first output the second block of comparison, the control input of the second block of elements And - with the output of the element And, and the control input of the third block of elements And - with the second output of the third block of comparison.  2. The device according to claim 1, characterized in that the multi-row code to two-row code converter consists of L adder layers, where L is the number of clock cycles of the original matrix to a two-row code containing adder blocks of the same weight, consisting of single-row three-input adders, with data buses the corresponding weight of the inputs of the converter are connected to the corresponding inputs of the adders of the same weight of the first layer of adders, the outputs of the adders of the ζ-th block of the l-th layer (l = 1, 2, ..., L - 1) are connected to the corresponding inputs of the adders of the ζ-th lock of the (l + 1) -th layer, the outputs of the adders of the ζ-th block of the l-th layer are connected to the corresponding inputs of the adders of the (ζ + 1) -th block of the (l + 1) -th layer, the outputs of the sums and transfers of adders of the last layer connected respectively to the first and second outputs of the Converter.

Images