SU1073766A1 - Orthogonal signal generator - Google Patents

Abstract

ORTHOGONAL SIGNAL GENERATOR, containing a clock generator, first and second counters, a group of elements And, a modulo two adder and a trigger, with the output of the clock generator connected to the input of the first counter, outputs of the And elements connected to the inputs of a modulo two, the output of which is connected to the counting to the trigger input, which also, in order to simplify the design of the generator of orthogonal signals, it contains the register of the shift value of the Walsh function, the register shift value of the number of the Walsh function, frequency divider, d a modulo two bitwise sum block and a direct code to inverse code conversion block, with the bits of the first counter and shift register of the Walsh function being connected to the first and second groups of inputs of the first block of bitwise modulo two, the overflow output of the first counter through the frequency divider is connected to the input of the second counter, the outputs of the bits of the second counter and the shift register of the Walsh function number are connected respectively to the first and second groups of inputs one unit of bitwise modulo two, outputs of the same-named bits of the first and second blocks of the same size (I modulo two of the same through the corresponding elements And connected to the inputs of the modulo two, the trigger output is connected to the information block of the converter unit g Direct code to the inverse, the control input and the output of which are, respectively, the control input specifying the type of sequence generated and the generator output from the orthogonal signals. 1 O5 a:

Description

The invention relates to automation and computing and can be used in devices designed for digital signal processing. A device is known which can be used to form N orthogonal signals containing (N -1) switch, (N -1) shift registers and (N-1) delay lines Cl. However, the known device is characterized by large hardware redundancy and complexity of switching circuits. The closest technical solution to the invention is an orthogonal signal generator comprising a clock generator, a discrete interval counter, a Walsh function number counter, an AND group of elements, a modulo two adder, a trigger, and the single outputs of all bits of the discrete interval counter are connected to the first inputs And elements, and the unit outputs of the counter Walsh function numbers are connected to the second inputs of the And elements, the outputs of which are connected to the inputs of a modulo-two adder, the output of which is connected to the input three 2J, The disadvantage of this generator is its complexity. The purpose of the invention is to simplify the generator of orthogonal signals. The goal is achieved by the fact that the generator of orthogonal signals, containing the clock generator, the first and second counters, the group of elements AND, the modulo two adder and the trigger, the output of the generator is also connected to the input of the first counter, the outputs of the elements and connected to the modulo two inputs, the output of which is connected to the trigger counting input, contains the Walsh function shift value register, the Walsh function shift value register, the frequency divider, two blocks of one-bit sum totaling two and the block prefix Formation of the direct code into the inverse, where the WELKHODES of the bits of the first counter and shift register of the Walsh function are connected respectively to the first and second groups of inputs of the first unit of modular two modulo two, the overflow output of the first counter in 000 001 010 Oil 10 © 0000 Oil oil oil oi

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010 iB as a composite signal in the invention, a signal of length N formed from a function is taken. Walsh half- 5

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1 0 0 the frequency divider is connected to the input of the second counter, the outputs of the bits of the second counter and the shift register of the Walsh function number are connected respectively to the first and second groups of inputs of the second unit of the modulo two summing two, the outputs of the same bits of the first and second blocks of the bit sum modulo two through the corresponding elements And connected to the inputs of the adder modulo two, the trigger output is connected to the information input of the block direct code to inverse control stroke and the output of which are respectively specifying control input form generated sequence generator and the orthogonal signal output, The figure is a functional diagram of the orthogonal signals. It contains a clock generator 1, a register 2 of the shift value of the Walsh function, a counter 3, blocks 4, 5 of modal two bitwise, a group of 6 elements AND, a counter 7, a register 8 of the shift value of the Walsh function number, a frequency divider 9, a modulo two 10, trigger 11, direct code-to-invert code block 12. The basis of the orthogonal signal formation in the invention is the dyadic shift of the composite signal. The algorithm of dyad shift of a sequence of eight elements is the following. To obtain a dyadically moved sequence, the sequence number of each element of the source sequence, written in binary form, must be added together modulo two with the value of the dyadic shift, also written in binary form. Below is an example of a dyadic shift into three sequences of eight elements 0 101 llOilll 000 0 1 1 l Oil Oil size system (Eoi N (2 - ") i The composite signal is constructed by repeating each Function 4 times, written as a series of characters, with a mandatory inversion of the function in one of 4 repetitions. The composite signal of length N 16 from the full Walsh function system of size n 2 has the form + + + + + + - + - + - + - + The dyadic shift of this signal gives 16 orthogonal 0: ++++++ signals - + - + - + - + 1: + + + + + --- + - + - + + 2: + + + + - + + + + + + - ++ 3: + + + + -.- + + - + - + + - + 4: ++ - +++++ - ++ - + 5: ++ - ++++ - ++ - + - + 6: - + 4- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + : - + - + - ++ - ++++++ - 10: + - + - + + - + + + + - + + 11: - + - ++ - +++++ - ++ 12: + - ++ - + - ++ - ++++ 13: - + + - + - + + + - + + + 14: - + + - + - + --- + + + + + + 15: + - + - + -. + - + + + + + + The dyadic shift value is equal to the sequence number of the corresponding orthogonal signal. In this case, if the sequence number is written in binary form, then K is the low-order bits of the number, where (c – sx determine the dyadic shift of the elements inside the Walsh function. The unit in (K + l) and (K + 2) bits means changing the position of the inversion of the Walsh functions in the dyadno-shifted composite signal. The values of the binary digits of the number, starting with (K + 3) and older, determine the magnitude of the dyadic shift of the Walsh functions of the composite signal. Forming the Walsh functions in the proposed generator is based on the bottom of the multiplication of the values of the discrete interval by the order of The Walsh function number and convolutions of this product are modulo 2. A dyadic shift of the composite signal can be performed if the corresponding dyadic shift value written in binary form is modulo two to the values of the discrete interval and the sequence numbers of the Walsh function. the values of the discrete interval are added modulo two to the lower digits of the dyadic shift value, and to the order number of the walsh function the most significant ones are added, starting with (K + 3), the bits of the binary representation of the dyadic shift value. The generator of orthogonal signals works as follows. In the initial state, counter 3 (argument), divisor 8 (by four), counter 7 (Walsh number functions) are in the state of all units. In register 2 and register 8, the values of the dyadic shift of the elements of the Walsh function and the values of the dyadic shift of the Walsh functions themselves are written, respectively. The first clock pulse coming from the generator output of 1 clock cycles to the counting input of the counter 3 transfers the counter 3, the divider 9 (to four) and the counter 7 to the zero state. The zero state of the counter 3 and the dyadic shift value of the elements of the Walsh function, recorded in register 2, add up modulo two B in block 4. As a result, the value of the discrete interval is formed, from which the diad-shifted composite signal begins to form. Zero state of counter 7 is incremental Modulo two in block 5 with the dyadic shift of the Walsh functions recorded in register 8. As a result, the number of the Walsh function that is first in the generated orthogonal signal is obtained. The contents of blocks 4 and 5 are bitwise multiplied by elements of AND group 6. In modulo 10 modulo two the resulting products are added modulo two and the result of the addition determines the state of trigger 11, the output signal of trigger 11 converts the direct code to inverse block 12 to the output of the device as the first value of the Walsh function with which the generated orthogonal signal starts. The second clock pulse increases the contents of counter 3 by one. At the same time, the contents of counter 7 remain unchanged. This ensures the formation of the next value of the discrete interval with the same Walsh function number. Similarly, all values of the first Walsh function are formed during the P clock. On the (n + 1) clock cycle, the counter 3 goes to the zero state, in the divider 9 one is recorded, the counter 7 remains in the zero. condition. Thus, the re-formation of the first Walsh function begins. Further, this function is repeated for the third and fourth time. At (4p + 1) clock cycle, counter 3 and divisor 9 go to the zero state, and counter 7 records the first unit a.,. which determines the number of the second Walsh function, a 4-fold formation of the values of the second Walsh function will begin, after which the second unit is sent to counter 7 and the number of the third Walsh function is generated. So, during the N cycles, a fully orthogonal signal is formed. On the last 4p2 clock cycle, counters 3 and 7, divider 9 go to the state of all units. From the next clock cycle, the orthogonal signal is re-formed if registers 2 and 8 do not change the value of the dyadic shift. The inverse of the Walsh function occurs in block 12 when the inversion signal is applied to the control input according to the dyadic shift algorithm. The simplification of the design of this generator compared to the prototype is achieved thanks to half the size of the registers used, the modulo-two adder and the number of elements I.

Claims (1)

ORTHOGONAL SIGNAL GENERATOR, comprising a clock generator, first and second counters, a group of AND elements, an adder modulo two and a trigger, the output of a clock generator being connected to the input of the first counter, the outputs of AND elements connected to the inputs of an adder modulo two, the output of which is connected to a counting trigger input, characterized in that, in order to simplify the design of the orthogonal signal generator, it contains a register of the magnitude of the shift of the Walsh function, a register of the magnitude of the shift of the Walsh function number, the frequency divider, two time blocks modulo two summation sums and the direct code to inverse conversion block, the outputs of the bits of the first counter and the shift register of the Walsh function are connected respectively to the first and second groups of inputs of the first bitwise summation block modulo two, the overflow output of the first counter through the frequency divider is connected to the input of the second counter, the outputs of the bits of the second counter and the register of the shift value of the Walsh function number are connected respectively to the first and second groups of inputs of the second block of summing modulo two, outputs of the same bits of the first and second blocks of bitwise summing modulo two through the corresponding elements AND are connected to the inputs of the adder modulo two, the trigger output is connected to the information input of the direct code to inverse conversion unit, the control input and output of which are respectively the control input of the job of the form of the generated sequence and the output of the orthogonal signal generator. SU. „, 10737>