SU383044A1 - DEVICE OF MULTIPLICATION OF SEQUENTIAL - Google Patents

Description

The invention relates to computing and can be used in digital computers and data processing devices.

The known devices for multiplying consecutive actions for number systems with a base of more than two form a partial multiplication signal by sequentially multiplying the multiplier digit by all digits of the multiplicable, taking into account at each step the transfer signal from the previous multiplier of one-digit digits, or when generating signals of one-digit digits, they remember all transfer signals of products of one-digit digits and then sum them with the signal of the accumulated sum of partial products.

However, the known multiplying devices. For number systems with a base greater than two, they have a complex device, due to the need to carry out operations with transfer signals when generating a partial work signal, and operations with transfer signals usually result in a decrease in the speed of operation of the devices.

The purpose of the invention is to simplify the multiplication device.

This is achieved by the fact that blocks of switching of outputs of bits of the register of multiplicand are entered into it, with the outputs of each pair

adjacent multiplicable bits through switching blocks are connected to the second input of the corresponding shaping unit, both outputs of which are connected to the inputs

adjacent bits of the register of partial products in such a way that adjacent blocks correspond to adjacent pairs of register bits, and the third and fourth outputs of the control unit are connected to the second inputs of the odd and even switching blocks, respectively.

The proposed multiplication device (see drawing) consists of register 1 multiplier, register 2 partial products, which is simultaneously accumulating adder, register 3 multiplicand, blocks 4 forming a single-digit digit product, blocks 5 switching outputs of the bits of the register multiplicable 6 and control 6 . The outputs of each pair of mixed multiplicable bits through the switching blocks of the outputs of the register of the multiplicable are connected to the input of one of the blocks of forming the signal of the one-digit digits, the second

the inputs of all the units of forming the signal of one-digit digits are connected to the output of the extreme bit of the register of the multiplier (major or minor), depending on the adopted variant of the operation

multiply, starting with a higher or lower

multiplier multipliers). Each unit of generating a one-digit digit product has two outputs: the output signal of the higher bit of the product and the output of the signal of the lower bit. If these blocks are presented in one row, and their sequence coincides with the sequence of bits of the register of the multiplicand (taking into account the connection with the blocks of switching of the bits of the register of the multiplicand) and the output of the high bit of the output is placed from the side facing the high bits of the result, then all the outputs of the signal forming units of the products, which at the same time have an alternating sequence of outputs of the senior and junior bits of the product, are connected to the inputs of the register of partial products Denia porazr bottom. The control unit is connected to the multiplier register, the partial product register, the output switching blocks of the multiplier register, and the generation unit for the generation of a one-digit digit.

The proposed device works as follows.

The signals of the numbers that need to be multiplied are taken into registers 1 and 3, then block 6 connects the outputs of odd register bits 3 to the inputs of blocks 4 using blocks 5. Then, using the signal from block 6, blocks 4 feed to the input of register 2 signals of one-bit dny digits. Upon completion of the summation of the previous result, stored in register 2 with the signals received from blocks 4, block 5 sends a shift signal to register 2 by one bit (the shift direction in registers 1 and 2 is determined depending on the chosen multiplication option ), at the same time, block 6 switches the register bit outputs with blocks 5: 3 to pass 4 blocks of input from the even bits of register 3 and repeats the output of signals from blocks 4 to register 2. After the summation in register 2 is finished, block 6 shifts si Nala multiplier stored in register / on one bit and the entire sequence is repeated oleratsy first. The termination of the operation is determined at the end of the formation of the last partial product, when a shift was made in the / register, which placed the signal of the last digit of the multiplier in the bit connected to the input of blocks 4.

Subject invention

A sequential multiplication device containing a multiplier register, a partial product register, a multiplicative register, single-digit product formation blocks and a control unit, the first output of which is connected to the partial product register, and the second output is with the multiplier register, the output of the high (low) bit which is connected to the first inputs of the formation blocks, characterized in that, in order to simplify the device, it contains blocks for switching the outputs of the register of the multiplicand, and outputs Each pair of adjacent multiplicable bits through switching units is connected to the second input of the corresponding flea formation, both outputs of which are connected to the inputs of the adjacent bits of the partial product register, the third and fourth outputs of the control unit are connected to the second inputs of odd and even switching units, respectively.