SU780000A1 - Converter of binary code into binary-decimal code of degrees, minutes and seconds - Google Patents

Description

(54) BINARY CODE CONVERTER TO BINARY DECODE DEGREES CODE, MINUTES AND SECONDS

one

The invention relates to the field of automation and computing technology and can be used in the construction of binary-decimal converters .5

The known converter of binary code into binary-decimal code of degrees, minutes and seconds is l containing a binary-decimal-sixth counter, a pulse generator, 10 two AND elements, two pulse distributors, two OR elements and a decoder

The disadvantage of this converter is its complexity and low. tS speed.

The closest solution to this problem by the technical nature and circuit design is converter 2, which contains an equivalent encoder, serially connected accumulative adders, whose inputs are connected to the outputs of the equivalent encoder, and the outputs are the outputs of the converter, the element NOT, the pulse generator and the pulse distributor, whose outputs are connected to the clock inputs of the encoder equivalents, the last output of the distributor

The pulse pulse is NOT connected to the first input of the first element I, the second input of which is connected to the output of the pulse generator, and the output is connected to the input of the pulse distributor, the information inputs of the equivalent encoder are connected to the information inputs of the converter.

A disadvantage of the known converter consists of relatively low speed.

The aim of the invention is to increase speed.

The set point is achieved by converting a binary code into a binary-decimal code of degrees, minutes and seconds, containing an equivalent encoder, serially connected boiling adders, the inputs of the second are connected to the outputs of the encoder of equivalents, and the outputs are outputs of the converter, the first the element AND, the element NOT, the pulse generator and the pulse distributor, the outputs of which are connected to the clock inputs of the encoder equivalents, the last output of the pulse distributor through the element is NOT connected to the first th input of the first

element And, the second input of which is connected to the output of the generator for pulses, and the output is connected to the input of the pulse distributor, informational, the inputs of the equivalent encoder are connected to the information inputs of the converter, additionally contains the second element And, the first and second registers and comparison circuit, the first and second groups information inputs of which are connected to the outputs of the first and second registers, respectively, the outputs are connected to the switching inputs of the equivalent encoder, and the control input of the connection comparison circuit The second input element is connected to the output of the pulse generator, and the second input of the second element is connected to the last output of the pulse distributor, the inputs of the second register are connected to the outputs of the first register, the inputs of which are connected to the corresponding bits of the information inputs of the converter.

The block diagram of the proposed Converter shown in the drawing.

The converter contains 1 pulse generator, first AND 2 element, 3 pulse distributor, encoder 4 equivalents, accumulative adder 5 seconds, accumulative cyNBviaTop b minutes, accumulative adder 7 degrees, information inputs 8 of converter, information outputs 9 of converter, element 10, second element 11, first register 12, second register 13, comparison circuit 14. The output of the pulse generator is connected to the first input of the first element And, the output of which is connected to the input of the pulse distributor; the outputs of the remote pulse pulse are connected to the control inputs of the equivalent encoder, and the high output of the pulse distributor is also connected to the second input of the second element AND and through the element NE of the second input of the first element And, the second input of the second element And is connected to the output of the pulse generator, the output of the second And is connected to the control input of the comparison circuit, and the outputs of the comparison circuits are connected to the clock inputs of the GG circuit, whose information inputs are connected to the corresponding and the converter inputs, the outputs of the first register are connected to the first information inputs of the comparison circuit and, via the second register, to the second infrastructural inputs of the comparison circuit, dirMay — inputs of the first 1st junction: eHbi and the inputs of mlr2e ip & r Ddifferent encoder, and the 15th interface and the inputs of ml§2e ix & r dpc encoder, the 15th interface and the inputs of the comparison circuitry the ego is connected to the inputs of the accumulator. adders of degrees, minutes and seconds; the overflow outputs of the accumulative seconds and minutes of the connection with the transfer inputs of the adder, respectively, minutes and degrees, and the information outputs of the accumulative degrees, minutes and seconds are connected to the corresponding outputs of the converter.

Accumulative suvviators of seconds, minutes, and degrees are based on the well-known binary-decimal adders.

DZU with a volume of n + 1 4t bit numbers can also be used as a generator of bit weights, where n is the number of bits of the word being transformed, am is the number of decimal bits of the angle value in degrees, minutes and seconds (weighting factor of the least significant bit available in DZU in direct and additional code).

0 The converter operates as follows.

The conversion begins by zeroing the cumulative adders and pulse distributor. In this case, the element and 2. opens, and the logical output 1 is established at the first output of the pulse distributor. 11 the exporter ratios, when 1 arrives at its first input and, when O or 1 is present, in the first position, the word being transformed generates, respectively, a zero or pre-decimal weight code the first bit of the word being transformed.

The code for the weight of the least significant bit of the word being converted is written in the memory accumulator. . The clock pulse from the generator through the open element AND set-. 1 at the second output of the pulse distributor, and the value of the binary-decimal code for the weight of the second bit of the word being converted is summed with the value of the code of the first bit and the sum is written in cumulative cyNwaTope.

Thus, the summation of the binary-decimal codes of the discharge weights of those digits of the transformed word, the value of which is equal to one, is made.

When set to 1 at the last output of the pulse distributor, the first element I closes and does not pass clock pulses to the distributor, and the binary output of the device sets the binary-decimal code, minutes and seconds, corresponding to the code being converted. The second element And opens, and the clock pulses of the generator begin

0 arrive at the control input of the comparison circuit. The comparison circuit compares the current value of the least significant bits in the first register with the contents of the second register, where

5 stores the previous value of the jun

Claims (1)

Claim A converter of a binary code to a binary decimal code of degrees, minutes, 30 minutes, and seconds, containing an equivalent encoder, sequentially connected accumulators, the inputs of which are connected to the outputs of the equivalent encoder, and the outputs are 35 outputs of the converter, the first AND element, the NOT element, oscillator pulses and the pulse distributor, the outputs of which are connected to the clock inputs of the encoder equivalents last output pulses via a distributor element is coupled to the first input of the first aND gate, the second ₄ the path of which is connected to the output of the pulse generator, and the output is connected to the input of the pulse distributor, the information inputs of the equivalent encoder are connected to the information inputs of the converter, characterized in that, in order to increase speed, the second element And, the first and second registers and the comparison circuit are introduced into it , the first and second groups. the information inputs of which are connected to the outputs of the first and second registers, respectively, and the outputs are connected to the switching inputs of the equivalent encoder, and the control the comparison circuit is connected to the output of the second element And, the first input of which is connected to the output of the pulse generator, and the second input of the second element And is connected to the last output of the pulse distributor, the inputs of the second register are connected to the outputs of the first register, the inputs of which are connected to the corresponding bits of the information inputs of the converter .