SU993243A1 - Angle binary code to degree bcd code converter - Google Patents

Description

the reset inputs of the control unit, the launch output of the nomadic is connected to the second information input of the primary switch, the control input of which is connected to the high-level output of the binary counter, to the transfer input of the adder and the control input of the second switch-disconnector, the information input of which is connected to the output of the counter and the first and second outputs of the second switch are connected respectively to the addition and subtraction inputs of a binary-decimal counter, whose information input is connected to the output of the memory unit, the low-order bits and the high-level input of which are connected. respectively, with the sum outputs and transfer output of the adder, the first group of inputs of which is connected to the information inputs of the high-order converter / logic zero input of which is connected. with the second group of inputs adder.

The control unit contains a trigger delay element, an H-OR element, an AND element and an OR element, the first and second inputs of which are, respectively, the first and second reset inputs of the α-control unit, the start input of which is connected to the first input of the AND-OR element with the element input delay, the output of which is the start output of the control unit and is connected to the third input of the OR element and the second input of the AND-OR element, the output of which is connected to the R input of the trigger, whose C input is connected to the output of the OR element, and the output of the trigger is connected to the first The input element is AND, the second input of which is the clock input of the control unit, and the output of the AND element is the clock output of the control unit, the second input input of which is connected to the third input of the AND-OR element.

FIG. 1 shows the block diagram of the converter of the binary code of the angle into the binary-decimal code of degrees; in fig. 2 is a block diagram of a control unit; in fig. 3 is a diagram of the correction counter.

FIG. 1, the following symbols are used: binary counter 1, adder 2, memory block 3, switches 4 and 5, control block 6, correction counter 7, binary-decimal counter 8, inputs 9 of the upper digits of the angle code, inputs of the 10 lower digits angle code, clock input 11, start input 12, output 13 of the most significant bit of counter 1, outputs 14 and 15 of overflow of counter 1, output 16 carry totalizer 2, output 17 of the code of sum totalizer 2, outputs 18 and 19 of the control unit output 20 of the correction counter and code output 21 of the binary-decimal counter 8. Block 6

control (Fig. 2) contains a trigger 22, delay element 23, element OR 24, element AND-OR 25, element. AND 26. Correction counter 7 (Fig. 3) contains counter 27, elements AND 28 and 29.

The Converter operates as follows.

The converter performs the binary code conversion of the n-bit code of the angle oC to the binary-decimal K1ed (% degrees.

With l-12, the binary code quantum weight is Aoi360 / 2 sr .51b,

and the binary decimal point weight is selected

equal to D |% b; gO, 1

I am for the conversion code

d divided into parts

A a a a

-WI

oc, f + e-2

ABOUT)

X and;

6L.xdL, -ai-l

de

, -. th- | ",

a-v

codes.

formed by m most-significant and p- (n-m) low-order bits of a code, respectively; ol, T-i, 0i bit digits of codes

i, -.

The proposed converter (Fig. 1) is listed for p-12, t-.

At the input 11 of the converter, the clock pulses of the TYPE arrive, at the input 12 - the pulses And 12. of the start, and at the inputs 9 and 10 - the codes / y and co. responsibly.

Memory block 3 generates a binary-decimal code f (.) By code f I generated by adder 2 on the basis of odnogo1ddeni

f $ -., (1},

where is the bottom digit of the elder

code bit counter 7 presets the pulse-code CHICK 0 binary code, defined by the ratio

 e, vu-e) e, C)

in binary discrete pulse number code so that the price of each pulse is equal to O, 1.

The conversion is performed by prohibiting the arrival at the output of d 20 of every eighth impulse of the CHICK c, p (51 since during the sweep time of the code

 to the maximum value, determined by quanta, should be issued- "112 pulses of a binary-decimal number-pulse code.

The control unit 6 is designed to form a sequence of signals synchronizing the operation of the converter in time.

Before the start of the conversion cycle, the converter contains the information of the previous cycle.

The conversion cycle starts with the arrival of the pulse I 12 of the trigger, according to which codes B to (NI) are entered into the counters 1 and 8, respectively, trigger 22 and Counter 27 are set to the zero state, an output is formed at output 19 through r, and 19.

With the end of AND 19, the trigger 22 goes into a single state and allows the TYPE to pass to exit 18. CHICK & from output 18 through switch 4 enters counter 1 for subtraction at (on addition for & 1), and through counter 7 corrections and switchboard 5 to counter 8 on addition for & sQ (subtraction at 9 -I).

With the end of the pulse AND 15 overflow of the counter 1 to the minus of the pulse AND 14 overflow to the plus the arrival of the TYPE is prohibited, g in the counter 8 is an interrogation code

If counter 1 overflows into minus, the converter performs the extra conversion cycle, which is pre-corrected by AND 19.

From the above, it follows that the duration of the conversion cycle can be determined by the expression

jpH

t4)

T "t-u

The duration of the prototype conversion cycle is determined by the expression

Tnpfil-i (B).

Compare (4 and (5), we get the estimate ...

TPD. aa. „-f -2igt- 2 - -

those. for t-C

, P1

Thus, the proposed mouth-; The solution has a higher speed.

Claims (2)

1. The converter of the binary code of the angle into the binary-decimal code of degrees, which contains the binary counter, the correction counter, the binary-decimal counter, the outputs of which are the outputs of the converter, the information inputs of the lower bits of which are connected to the information inputs of the binary counter, about. Ji. and the fact that, with. to increase speed, an adder, a memory unit, first and second switches, and a control unit, the clock input of which is a clock input of the transformer, the startup input of which is connected, are entered into it. with inputs for receiving the daoichny and binary-decimal counters with the reset input of the correction counter and the start input of the control unit, the clock output of which is connected with a counting input midrange correction and the first information of the first. switch, the second and second outputs of which are connected respectively to the addition and subtraction inputs of a binary counter, whose overflow outputs are connected to the first and (second reset inputs of the control unit, the start output, which is connected to the second information input of the first switch, control input which is connected to the output of the high bit of the binary counter, to the transfer input of the adder and to the control the input of the second switch, the information input of which is connected to the output of the correction counter, and the first and second outputs of the second Eora switch are connected respectively to the inputs adding and subtracting the binary-decimal counter, the KOToi oro information input is connected to the output of the memory block, the low-end inputs and the high-level input of which are connected to the sum output and the transfer output of the sixth output, the first group of inputs of which are connected to the high-level information inputs converter bits,. input logical zero of which is connected to the second group of inputs of the adder. 2. The transducer is about the t and in that the control unit contains a trigger, zyklyunt. delays, element AND-1, element AND and element or, the first and second inputs of which are respectively the first and second reset inputs of the control unit, the start input of which connected to the input terminal of the AND-OR element and the input of the delay element, the output of which is the start output of the control unit and connected to the third input of the OR element and the second the input of the I-SH1I element, the output of which is connected to the trigger input, whose C input is connected to the output of the 1ШЫ element, and the trigger output is connected to the first input of the AND element, the second input of which is the contact input of the control unit, and the output of the AND element is the clock output of the control unit, the second reset input of which is connected to the third inlet of the AND-OR element. . Information sources, accepted in examination 1. Author's Certificate of the USSR 756403, cl. G06F 5/02, 1978. 2. Authors certificate of the USSR 760084, cl. G06P 5/02, 1976. (rig.E