SU943704A1 - Binary to digital pulse code converter - Google Patents

Description

(5) BINARY CODE CONVERTER

IN PULSE CODE

one

The invention relates to automation and digital 1 computer technology and can be used in the construction of converters in devices for receiving and transmitting discrete messages, as well as in measuring devices.

A known converter of a binary code into a sequence of pulses, containing a register, AND elements, single-oscillators, differentiating chains, a common OR element, OR output elements, memory and control triggers 1.

The disadvantages of the known converter are its complexity and a large amount of equipment.

The closest to the invention in technical essence and circuit construction is a binary code converter into a number-impedance code containing a counter, each bit of which has main and auxiliary triggers, mode trigger

and the element I. In addition, the well-known converter contains a prohibition trigger 2.

The disadvantages of this converter are the control complexity with the device and low reliability due to the large number of external connections.

The purpose of the invention is to simplify the mouth (of the device and increase its reliability.

The goal is achieved by converting a binary code into a pulse-pulse code containing a counter, each bit of which has main and auxiliary triggers, a mode trigger, an AND element whose first input is connected to a single output of a mode trigger, the second input is connected to a clock input the converter, with the clock input of the mode trigger and the clock input of the main trigger of the zero discharge of the counter, the output of the element I is the converter, zero and one outputs of the main trigger of the 1st time yes counter (i 0-p), where n is the number of bits of the input code, are connected respectively to the first one and zero inputs, the auxiliary trigger i-ro of the counter, the single and zero inputs of the main trigger i-ro yes are connected respectively to single and zero, the outputs of the auxiliary three | - gera i-ro bits, the single output of the main trigger of the n-th bit of the meter connected to the control input of the mode trigger, additionally contains two input elements AND-NOT, a group of n elements 2I-OR and the element is NOT-NULL., the output of which o is connected to the reset inputs of the main triggers from the 1st to the nth digit, with the input of the initial installation of the main trigger units of zero discharge by the initial installation input zero of the auxiliary zero-discharge trigger, inputs of the initial installation of the auxiliary trigger unit from the 1st to The 5th bit and the reset input of the mode trigger, the zero output of which is connected to the first inputs of the 2I-OR group elements and the first inputs of the first and second AND-NOT input elements, the second inputs of which are information inputs of the converter, and the outputs are connected respectively to the second zero and second single inputs of the auxiliary zero-trigger trigger, the clock input of which is connected to the clock input of the converter and to the second inputs of elements 2I-OR of the group, the third inputs of which are connected to the single output of the mode trigger, fourth input j-ro (j 1 - n) of element 2I-OR of the group is connected to the single output of the main trigger (jl) -ro of the discharge, to the second single input of the auxiliary trigger of the j-ro discharge, and to the j-th input of the NAND null element, and the output of the j-ro element 2I-OR group is connected to the clock inputs of the main and auxiliary three | ge j-ro bit, zero output of the main trigger {j -) - ro bit is connected to the second zero input of the auxiliary j-ro bit trigger.

In the proposed converter, the auxiliary trigger contains

the first and second AND-OR-NOT elements whose outputs are the single and zero outputs of the auxiliary trigger and are connected respectively to the first inputs of the second and first AND-OR-NOT elements, the second inputs of which are combined and are the clock input of the auxiliary trigger, the third inputs The first and second elements AND-OR-NOT are, respectively, the first single and zero inputs of the auxiliary trigger, the fourth inputs of the first and second elements AND-OR-NOT are the second

the single and zero inputs of the auxiliary trigger, the fifth and sixth inputs of the first AND-OR-HE element are connected and are the input of the initial installation of the auxiliary trigger.

The drawing shows the block diagram of the proposed Converter.

The binary-to-pulse code converter contains counter 1, each bit of which consists of main trigger 2 and auxiliary trigger 3. The main and auxiliary triggers consist of two AND-OR-NOT elements and 5. The result of the conversion is received

conversion output 6. Between the bits of counter 1, a group of elements 2I-OR 7 is included. In addition, the converter contains a trigger of mode 8, input elements AND-HE 9-10, element AND-NOT 11 zeroing, element 12, informational inputs 13-1 of the converter.

Converter code to the number of pulses works as follows.

In the initial state, the zero bit of counter 1 is in a single state, and the remaining bits of counter 1 and switch trigger 8 are in the zero state, while permitting the passage of information that goes to inputs 13 and 14 in the vapor phase code, through the input elements AND-NOT 9 and 10 to the information inputs of the counter 1 and set the latter to the shift register mode. The incoming information is shifted by the clock, and when the last bit of information is received, the unit recorded in the zero bit of the counter 1 in

the initial state, reaching the high-order bit, enables switching the trigger mode of the latch type, which switches on the falling edge of the clock signal, prohibits the passage of information to the input of counter 1, switches the latter to the counting mode and allows the clock signals to pass. As soon as the number of pulses passed at the output of the converter reaches a value of the return code, when recorded in counter 1, all bits of counter 1 are set to one, and a low level signal is generated at the output of the null-AND-NO element, which sets the elements of the converter in the initial state, thus preparing it to receive a new information code.

The proposed code to pulse converter as compared to the prototype allows reducing the number of IC cases with an 8-bit counter from 37 to 27 in the case of building a converter on an IC series, as well as reducing the number of inputs and simplifying the control of the converter.

Claims (2)

1.- Binary code to pulse-pulse code containing a counter, each bit of which has a main and auxiliary triggers, a mode trigger, an I element, the first input of which is connected to a single trigger output; mode, the second input is connected to the clock input of the converter, to the clock input of the mode trigger and to the clock input of the main trigger of the zero discharge of the counter, the output of the And element is the output of the converter, zero and single outputs of the main trigger of the t-ro discharge of the counter (o ), where n is the number of bits of the input code, are connected respectively to the first one and zero inputs of the auxiliary trigger i-ro of the counter, the single and zero inputs of the main trigger i-ro bits are connected respectively to one and zero you odes auxiliary trigger i-ro discharge, the main trigger output unit, the n-th discharge .schetchika connected to the control input of the flip-flop mode, characterized in that, in order to increase reliability prescience generator, it contains two AND-NOT input elements, a group. of n 2I-OR elements and an NAND zeroing element, the output of which is connected to the reset inputs of main triggers from the 1st to the nth digit, with the input of the initial installation of the basic zero-trigger unit, the input of the initial. setting zero of the auxiliary trigger zero bit, with the inputs of the initial installation of the unit of auxiliary triggers from the 1st to the nth digit and the reset input of the mode trigger, the zero output of which is connected to the first inputs of the 2I-OR group elements and the first inputs of the first and second input elements AND-NOT second inlets the dads of which are infbruction inputs the converter, and the outputs are connected respectively to the second zero and single inputs of the auxiliary zero-bit trigger, the clock input of which is connected to the clock .the converter input and with the second inputs of elements 2I-OR groups, the third inputs of which are connected to the unit output of the mode trigger, the fourth input j-ro () of the element 2I-OR groups are connected to the single output of the main trigger (jl) -ro of the discharge, with the second single input of the auxiliary trigger of the j-ro discharge and with the j-th input of the N-NU element, and the output of the J-ro element 2I-OR the group is connected to the clock inputs of the main and auxiliary j-ro bit triggers, zero output of the main trigger (j) ro bit. - connected to the second zero input, auxiliary trigger j-ro bit. 2. The converter according to claim 1, similar in that the auxiliary trigger contains the first and second AND-OR-NOT elements, the outputs of which are the single and zero outputs of the auxiliary trigger and are connected respectively to the first inputs of the second and first elements AND OR-NOT, the second inputs of which are combined and are the clock input of the auxiliary trigger, the third inputs of the first and second AND-OR-NOT elements are respectively the first one and zero inputs of the auxiliary trigger, the fourth inputs of the first and second elements AND-OR-NOT are second the single and zero inputs of the auxiliary trigger, the fifth and sixth inputs of the first AND-OR-NOT element are combined and are the input of the initial installation of the auxiliary trigger. Sources of information taken into account in the examination 1. USSR author's certificate number 415658, cl. G 06 F 5 / 0t, 1971. - 5 2. Authorskor certificate of the USSR No. 602936, class 06 F5M, 1976 (in prototype)