SU1084779A1 - Translator from binary code to binary-coded decimal code - Google Patents

Abstract

A BINARY BODY CONVERTER BINARY-DECIMAL, containing a pulse generator, a pulse distributor, a driver of equivalents and a binary-decimal accumulative adder, the outputs of which are the outputs of the converter whose information input is connected to the information input of the pulse distributor, the clock input of which is connected by a connector with a output of a converter with a pin. pulse generator, the output of the binary code of the pulse distributor is connected to the control input of the binary-ten accumulative sum, the information The inputs of which are connected to the outputs of the equivalent generator, the input of the reading of cycles and the preparation input of which are connected respectively to the output of the reading of cycles and to the output of preparation of the pulse distributor, the output of which is connected to the reset inputs of the generator of equivalents and the DAC accumulator, characterized in that in order to simplify it, in it the equivalent shaper consists of tetrads, each of which contains a register of signs of bits, a prohibition element and a measure adder, and each tetrade of the binary-decimal accumulative adder contains the intermediate amounts register, intermediate adder, OR element, code adder and prohibition element, the first and second inputs of which are connected respectively to the outputs of the third and fourth digits of the code adder, the first inputs of the second, third and fourth the bits of which are connected to the output of the OR element, the first and the second, whose inputs are connected respectively to the transfer output and the fourth discharge of the intermediate adder, the first inputs of all times The ports of which are connected to the outputs of the corresponding register bits of the intermediate sum, the control input and the reset input of which are, respectively, the control input and the reset input of the binary-decimal (L accumulative adder, the information inputs and outputs of which are respectively the second inputs of the intermediate adder and the outputs of the intermediate sum register, the inputs of the first, second, third and fourth bits of which are connected respectively to the outputs of the first bits of the intermediate adder and The code blocker, the output of the prohibition element 00, and the output of the third 4th digit of the adder of the code whose transfer output is connected to the transfer gate of the intermediate sum VJ of the next highest tetrada double: the same-decimal accumulative adder and the first input of the first digit of the code adder, the second the inputs of the first and second bits of which are connected to the output of the second bit of the intermediate adder, the output of the third bit and the transfer output of which are connected respectively to the second inputs of the third and fourth bits of the sum ora code, outputs the first, third and fourth bits of each tetrad cycles adder shaper equivalence

Description

the tone is connected respectively to the inputs of the second, third and fourth bits of the bit register of the bits of the control input of which is with the control input of the equivalent generator, the reset input of which is the reset input of the register of the bits of the bits, the outputs of the first, second and third bits of the Kofopogo are connected respectively to the first inputs of the second, third and fourth bits of the cycle adder, the second inputs of the third and fourth bits of which are connected respectively to the third and fourth bits of the third and fourth bits the register of features of bits and the first and second inputs of the prohibition element of the equivalent generator, the overflow output of the clock adder is connected to the input of the first discharge of the register of the bits of the next most significant equivalent of the equivalent frequency generator and the first input of the first bit of the timing matrix, the second inputs of the first and second bits which are connected respectively with the outputs of the first, third and third bits of the register of signs, bits, the outputs of the first, second and fourth bits of which, together with the output of the prohibition element and the equivalent shaper is the output of the tetrade shaper equivalents, input; the first discharge of the first tetrad of the equivalents shaper is the input to the preparation of the equivalent shaper.

The invention relates to automation, remote control and computing, and can be used in the construction of binary-to-binary converters.

Known Binary Converter | ego code in binary-decimal, containing a binary code counter of a sequential code, a decoder, a clock pulse generator, a weight equivalent counter, a comparison circuit, a repeat counter, a low-order prohibitor unit, a clock-prohibiting unit lj.

The disadvantage of this converter is the low speed, which is caused by the conversion of the number n. cycles, the repetition cycles of which are produced by the generator depending on the weight of the incoming bit (1,2,4, etc.).

The closest in technical essence to the invention is a binary-to-decimal binary converter, comprising a clock pulse generator, a pulse distributor, an equivalent driver, a binary-decimal adder, an intermediate sum register, a write signal former, and the inputs of binary-decimal summers are connected with the corresponding outputs of the driver equivalents, and the outputs are connected to the inputs of the register of intermediate amounts, the clock input of the pulse distributor is connected to the output of the generator ora pulses, binary output pulse distributor - to the control input dvoychvo-dec tichnogq

the adder, the clock read input and the preprocessor of the equivalent driver are connected respectively to the clock read output and the output of the pulse distributor preparation, the reset output of which is connected to the reset inputs of the equivalent former and the binary-decimal adder 2. Q A disadvantage of the known converter is the complexity of building the binary-decimal adders, since with an increase in the binary code size, the equipment of the distributor and equivalent generator, as well as the complexity of control, increase dramatically.

The aim of the invention is to simplify the converter.

The goal is achieved

0 in that in a binary-to-decimal converter, containing a pulse generator, a pulse distributor, a driver of equivalents and a binary-ten accumulative adder, the outputs of which are you: the transmitter of which the information input is connected to the information input pulse distributor

0 clock input of which is connected to: pulse generator output, output of binary code of pulse distributor is connected to control input of binary-decimal accumulator - adder, information inputs of which are connected to outputs of the driver of equivalents, clock read input and training input of which are connected respectively to

a clock read output and a pulse distributor training output, the reset output of which is connected to the reset inputs of the equivalent generator and the binary-decimal accumulative adder, the equivalent former consists of tetrads, each of which contains a register of signs of bits, a prohibition element and a clock adder, and each tetrad of the binary-decimal accumulative adder contains a register of intermediate sums, an intermediate adder, an element OR a code adder and a prohibition element, the first and second inputs of which are Connected respectively to the outputs of the third and fourth bits of the code accumulator, the first inputs of the second, third and fourth bits of which are connected to the output of the OR element, the first and second inputs of which are connected respectively to the transfer output and the output of the fourth digit of the intermediate adder, the first inputs of all the bits of which are connected to the outputs of the corresponding bits of the register of the intermediate sums, the control cad input and the reset input of which are respectively the control reset input of the binary-decimal cumulative adder, information inputs and outputs of which are, respectively, the second inputs of the intermediate adder and outputs of the intermediate sum register, the inputs of the first, second, third and fourth bits of which are connected respectively to the outputs of the first bits of the intermediate adder and the code adder, the output of the prohibition element and output of the third bit of the code adder, the transfer output of which is connected to the transfer input of the intermediate adder of the next highest tetrade of the binary-decimal accumulative the first adder and the first input of the first digit of the adder code, the second inputs of the first and second bits of which are connected to the output of the second digit of the intermediate adder, the output of the third bit and the transfer output of which are connected respectively to the second inputs of the third and fourth bits of the adder code, outputs the first, third and fourth bits of the adder of cycles of each tetrade of the equivalent former are connected respectively to the inputs of the second, third and fourth bits of the register of the signs of bits, control The third input of which is the control input of the driver-equivalents, the reset input of which is the input of the reset of the register of signs of bits, the outputs of the first, second and third bits of which are connected respectively to the first inputs of the second, third and fourth bits of the clock accumulator, the second inputs the third and fourth bits of which are connected respectively with the outputs of the third and fourth bits of the register of bit recognition and the first and second input elements of the prohibition of the equivalent generator, the output of overflows The adder of clock cycles is connected to the input of the first bit of the register of features of the next highest tetrade of the equivalent generator and the first input of the first bit of the clock accumulator, the second inputs of the first and second bits of which are connected respectively to the outputs of the first and third bits to the outputs of the first, second and fourth bits which, together with the output of the prohibitor of the equivalent shaper, are the outputs of the tetrad of the equivalent shaper, the input of the first discharge of the first tetrad of the equivalent shaper is with the input of preparation of shaper equivalents.

Fig. 1 shows the block diagram of the proposed converter in Fig. 2 — temporal relations of the code parcel and control signals.

The binary-to-binary binary code converter contains a pulse generator 1, a pulse distributor 2, a register of 3 bits signs, a 4-cycle adder, a intermediate sum register 5, an intermediate adder b, a code 7 adder, an equalizer suppressor element 8 for disabling weighing 2 with simultaneous presence at the second input of bit 2, the element OR 9, which is designed to collect bit 2 and the overflow signal of the intermediate adder b, and element 10 of the prohibition.

A register of 3 bits signs is assigned to store the current value of the binary bit as a binary-decimal equivalent.

The register 3, the adder 4 and the prohibition element 8 are used to convert the current value of the binary bit to the binary-decimal equivalent. .

Gregaster 5 intermediate sums is intended for storing the sum of the values of binary code bits in the form of binary-decimal equivalents.

The intermediate adder 6 is a binary adder and is designed to sum the current binary-decimal code bit value with the total value of the previously received code bits. Adder 7 is a binary decadal adder and provides, together with intermediate register 5, intermediate accumulator b, the elements of OR 9 and prohibit the formation of the binary-decimal equivalent of the binary code. The input information in the form of sequential code parcels is fed to information input 11 of the converter. The pulse distributor 2 generates four signals, the time relationships of which are shown in FIG. 2: at output 12, clock read pulses (clock pulses for the code send time), and output for preparing the first D input of the first bit of the register 3 (pulse of the beginning of the code send ); on exit. 14 pulse setting in O registers and 5; output 15 pulses binary code (code parcel). I. The result of the conversion is formed at the outputs 16. The register of 3 signs of bits, the adder 4 tacho and the element 8 of the Prohibition in combination form a tetrad forming 17 equivalents. Register 5 Intermediate Amounts, Intermediate Adder 6, Code Adder, Elements OR 9 and Prohibition 10 together form a tetrad of two 1-ten six accumulative sum 18 i. The binary-to-binary converter works as follows. The input of the distributor 2 pulses receives the clock pulses of the generator 1 pulses and code links to the input 11 (the younger ones will go ahead, and one parcel may contain several codes to be converted). A setup signal in O registers 3 and 5 prepares the transmitter to receive information. The pulse frequency at the moment of presence of the first register bit D-input of the register 3 impulses the beginning of the code parcel writes 3 units into the register, which corresponds to the value of the bit with a weight of 2 °. The next clock pulse doubles the value in register 3. When the value in the register of numbers is more than 8, adder 4 corrects the values of numbers in registers 3 and transfers the number 2. 10 to tetrad n + 1, where n is the number of tetrad The value of the current bit in the binary-tenth equivalent, formed by the former 17 equivalent, is summed by adders 6 with the previous bits, stored (Rimis In registers 5. The total value of the adders b goes through the adder 7 code to the information inputs of the register 5. The adder 7 converts numbers from O to 18 into a decimal equivalent. Transfer signal 2, Yu with the sum torus 7 is fed to the information input of the 1st bit of the adder of the tetrad b tether n + 1. Writing information to the register 5 is made by a pulse of the corresponding bit of the input binary code, if there is no input in the code of the bit, no entry is made to the register 5; truth is indicated by the j bot of the converter, depending on the incoming clock (T) (a sign of the current bit) and the code send bit / n, /, where i is the current bit number. Let us consider in more detail the operation of the converter for the binary code 11111 using the example of the Two Notebook — the principle of conversion extends to a binary sequential code of any length, coming in lower digits ahead. The first clock pulse from output 12 is the first bit of register 3 with a weight of 2 set (it is poured into the unit state H and is fed through the adder 4. to the D input of the second bit with a weight of 2 register 3 and through the adder b to the D input of the first bit yes with a weight of 2 ° register 5. A pulse of a code with a weight of 2 enters at output 15 and rewrites the value from the D input to register 5. From the output of the register, the single state of the first discharge enters output 16 and through the adder b to D - input of the first digit of the register 5. The starter 5 stores with a weight of 2 According to the second clock pulse a second time The register 3 with a weight of 2 is set to H, the state from the output of the second bit is fed through the adder 4 to the D input of the third bit of the register 3 and through the adders B and 7 to the D input of the second digit of the register 5. Pulse of the code discharge with a weight of 2, rewrites the value from the D inputs of the register 5 to the register itself. From the output of the register 5, the unit state of the first and second bits is fed to output 16 and through the adder b to the D-input of the first register bit 5, and through adders b and 7 - to the D-input of the second register bit 5. Register 5 stores i with a weight of 2 u2. By the third clock pulse, the third bit of register 3 with weight 2 is set to one, and its value through adder 4 enters the D-inputs of the third and fourth bits of register 3, and through element 8 of the generator shaper equivalent, adders 6 and 7 , “Prohibition element 10 with a weight of 2 arrives at the D-input of the third bit of the datalogger 5.2. The pulse of the discharge code with a weight of 2. rewrites the value from the D-inputs of register 5 into the register itself. From the register output, the unit state of the first, second, and third bits is output 16 and output via adder B is sent to the D input of the first register register 5, and through the adders 6 and 7 to the D input of the second discharge register 5 and through the adders ji 7 and the element 10 of the prohibition on the D-in of the third bit of the register 5. 1 gyr 5 stores with a weight of 2, 2 and 2 the fourth clock pulse sets the third and fourth bits of the register 3 into one state the value of the third and fourth bits are summed at adder 4, as a result, unit 10 is fed to the D input n The second bit is of the second tetrad of register 3, and the remainder is 10 (2 and 2) goes to the D inputs of register 3 of the first tetrad. The following information comes to the adder 6: from the register 3, the values of the weight are 2, while the value of the discharge with a weight of 22 in the presence of a discharge with a weight of 2 does not allow the element 8 of the prohibition; from register 5 the value of the bits is 2 °, 2 and 2 overhang 2. The value of the discharge with a weight of 12 ° goes through the adder to the D-input the first bit of register 5, the value of bits with weights 2 and 2 pitch with the corresponding bits of the adder 7, and the value of bit with weight 2 through the element OR 9 at the input of bits with a weight of 2, 2 and 2 adder 7.

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1 о 1 о As a result of summation on adder 7, the transfer unit of adder 7 (2 °. 10) enters the D-input of the first digit of the register B of the second tetrad, and the remainder weighing 2 through the prohibition element 10 enters the D-input of the third discharge register 5. At the input of register O1B 2 of two tetrads, bits with weights of 2 and 2 of the first tetrad and 2 ° of the second tetrad are prepared. The pulse of a code with a weight of 2 rewrites the value from the D inputs of registers 5 to the register itself. The code values from the registers 5 are fed to the outputs of 16 two tetrads and through adders B prepare the first bits of the register 5 of two tetrads, and through the adders 6 and 7 - the third bit of the register 5 of the first tetrad. Register 5 stores unit values of 2 and 2 in the first tetrad and 10 in the second tetrad. The work of subsequent tetrads in the conversion is similar. When the code message is less than the maximum set register 3, the adder 4 and the prohibition element 8 continue to work (the bits are being recalculated), but the register 5 is closed for conversion and stores the recorded number until the next code message. Thus, the proposed converter allows the conversion of a binary code of any length without increasing the amount of additional equipment, only the number of similar tetrads is increased. In addition, in the converter, the code is converted according to the bits of the incoming code, which shortens the conversion time, and the number of clock cycles is determined by the number of code bits.

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Claims (1)

Binary-to-decimal converter containing a pulse generator, a pulse distributor, an equivalent generator and a binary-decimal accumulator, the outputs of which are the outputs of the converter, the information input of which is connected to the information input of the pulse distributor, the clock input of which is connected to the output of the pulse generator, the output the binary code of the pulse distributor is connected to the control input of the binary decimal cumulative sum ·? a torus, the information inputs of which are connected to the outputs of the equivalent shaper, the clock reading input and the training input of which are connected respectively to the output of the clock reading and the pulse output of the pulse distributor, the reset output of which is connected to the reset inputs of the equivalent shaper and the binary-decimal accumulator, characterized in that, for the purpose of simplification, it consists of a generator equivalents tetrads, each of which comprises a register ¹ sign bits and sum element prohibition clock cycles, and each tetrad of the binary-decimal accumulative adder contains a register of subtotals, an intermediate adder, an OR element, a code adder and a ban element, the first and second inputs of which are connected to the outputs of the third and fourth bits of the code adder, the first inputs of the second, the third and fourth bits of which are connected to the output of the OR element, the first and second, whose inputs are connected respectively to the transfer output and the output of the fourth bit of the intermediate adder, the first inputs are all the bits of which are connected to the outputs of the corresponding bits of the intermediate sums register, the control input and the reset input of which are respectively the control input and the ® input of the binary-decimal accumulator totalizer reset, the information inputs and outputs of which are respectively the second inputs of the intermediate adder and the outputs of the intermediate sums register the inputs of the first, second, third and fourth bits of which are connected respectively with the outputs of the first bits of the intermediate adder and su a code matrator, with the output of the inhibit element and the output of the third bit of the code adder, the transfer output of which is connected to the transfer input of the intermediate adder of the neighboring senior notebook two two decimal accumulative adders and the first input of the first discharge of the code adder, the second inputs of the first and second bits of which are connected to the output of the second the discharge of the intermediate adder, the output of the third discharge and the transfer output of which are connected respectively to the second inputs of the third and fourth bits of the adder code, the outputs the first-, third- and fourth discharge cycles of each tetrad adder shaper equivalence SU. with the first inputs of the second, third and fourth bits of the clock adder, the second inputs of the third and fourth bits of which are connected respectively to the outputs of the third and fourth bits of the register of signs of bits and the first and second inputs of the inhibitor element of the equivalent shaper, the output of the overflow of the clock totalizer is connected to the input of the first bit of the register of signs of the bits of the next senior notebook of the shaper which are connected respectively with the outputs of the first and third bits of the register of signs, bits, the outputs of the first, second and fourth bits of which together with the output of the ele The shaper of equivalent shaper is the outputs of the tetrad of the shaper of equivalents, the input of the first discharge of the first tetrad of equivalent shaper * is the input of the preparation of the equivalent shaper.