SU1376106A1 - Analog-to-digital integrating device - Google Patents

Abstract

The invention relates to computing and can be used as an operating unit of analog and analog-digital computing systems, as well as in preprocessing devices and forms, in particular, in spectrum analyzers. The purpose of the invention is to simplify the device and extend the functionality by implementing the result storage mode. The device contains a voltage-to-frequency converter 1, a reversible counter 2, a digital-to-analog converter 3, a multiplication digital-to-analog converter 4, an IS-CROSS OR 5 element, a trigger 7, a decoder 18, an OR-NOT 6 element, AND-NOT elements 19-23, shaper 24 pulses. In an analog-to-digital integrating device, the voltage range at the analog output 12 of the device corresponds to the voltage range at the analog information input 15 of the device, and the width and format of the output digital signal are the size and format of the input digital signal. In addition, the device implements the mode of storing results by setting the zero signal at the device mode input 26. 4 things. C. (/) SOUd O5 .G

Description

The invention relates to computing and can be used in devices for preprocessing information, in particular in spectrum analyzers, and also as an operating unit of analog and analog-digital computing systems.

The purpose of the invention is to simplify the device and extend the functionality by implementing the result storage mode.

FIG. 1 shows the functionality of the analog-digital integrator circuit; in fig. 2 - temporary Diagrams of the operation of the reversible counter, trigger and decoder when performing the operation of summation in the reversible counter; in fig. 3 - the same, when performing the operation of subtraction in a reversible counter; 4 is a schematic diagram of a pulse former.

The analog-to-digital integrating device (Fig. 1) contains a voltage-to-frequency converter 1, a reversible counter 2, a digital-to-analog converter 3, a multiplying digital-analog converter 4, the element EXCLUDING IT OR 5, the element OR-NOT 6, trigger 7, the element AND 8, device clock input 9, digital input 10 of device initial conditions, digital output AND devices, analog output 12 of the device, control output 13 of the device, sign output 14 of the device, analog information input 15 of the device, sign input 16 of the device, first 17 input specifying device mode, decoder 18, five AND-NO elements 19-23, pulse generator 24, sign input 25 of initial conditions specifying device, the second input device 26 specifying mode, the digital information input device 27.

Pulse shaper 24 (FIG. 4 contains three AND-HE elements 28-30 and an integrating KS circuit 31, wherein the inputs of the AND-NE element 28 are the input and the output of the AND-NE element 30 is the output of the shaper.

The device operates in three modes: Preparation, Work and Storage of the result. The Prepare mode is set to single values of the signals at inputs 17 and 26 of the device and is used to set the initial conditions in the analog

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the digital integrating device. The initial conditions are represented by a direct code, the mantissa of which is fed to the digital input 10 of the initial conditions of the device and the sign to the sign input 25 of the initial conditions of the device. In the case of a single signal at input 17 of the device, the reversible counter 2 is transferred to the mode of receiving information from the setup input, which allows writing any p-bit code in its small section, submitting it to the input 10 of the device. At the most senior (n + 1) -th bit, a zero is written here, since the (n + 1) -th bit of the setup input of the reversible counter 2 is connected to the common point of the device. The unit value of the signal at the device input 17 also allows writing the sign of the initial conditions into the trigger 7, passing it to the device input 25. This uses the preset channel of the trigger 7, which includes the third 21, the fourth 22 and the fifth 23 AND-NOT elements. When the signal at the device input 17 goes from one value to zero (with a single signal at device input 26), the device switches to Run mode. The up / down counter 2 enters the counting mode and its contents change after the arrival of each pulse at its counting input.

These pulses are generated at the information output of the voltage-to-frequency converter 1 and, if necessary, are sharpened (shortened) by means of the signal former 24. The pulses at the output of the signal conditioner 24 are increments of the integral of the input effect of the device. The increment sign is formed at the sign output of the voltage-to-frequency converter 1 as one or another value of the logical variable. So, the zero value of this variable determines the increment of the positive value of the integral, and the unit value is the increment of the negative value of the integral. The value of the logical variable at the sign output of the voltage-to-frequency converter 1 controls the mode of the reversible counter 2, since the sign output of the voltage-frequency converter 1 through the first input of the EXCLUSIVE OR 5 element, the decoder 18 and the first AND-19 element are connected to the reverse sign input counter 2. The zero signal at the output of the first element NAND 19 transforms the reversible counter 2 into the summation mode, and the unit one into the subtraction mode. In the reverse counter 2, in this case, the current value of the integral mantissa from the input effect of the device in the forward code is formed. The sign code of the current value of the integral from the input action is formed in trigger 7, the forward output of which is the sign output 14 of the device. The mantissa of the input integral of the device is formed in the lower bits of the reversible counter 2, the set of outputs of which is the digital output 11 of the device, which together with the sign output 14 of the device forms a digital information (n + 1) bit output of the device. At the same time, the mantissa and the sign of the current value of the integral of the input action of the device are fed to the input of the digital-to-analog converter 3, the output of which produces the corresponding voltage applied to the analog output 12 of the device. In the older (n + 1) -th discharge of the counter counter 2, a signal logical unit when transferring from n younger bits. This transfer can be considered as an overflow of the discharge grid, so the output of the higher bit of the reversing counter 2 is connected to the control output 13 of the device. The appearance of a single signal at this output indicates the need to interrupt the computational process in the device in question and in the entire analog-digital computer system into which this device enters.

The formation of the direct code of the current value of the integral of the input action of the device in the reversible counter 2 and trigger 7 is performed using the element OR-NOT 6, the decoder 18, the first element AND-19, the second element-AND 20 and the element 8 The second code of the integral of the input action of the device in the reversible counter 2 and trigger 7 is illustrated by timing diagrams (Figs. 2 and 3). FIG. 2 shows the process of summation () in the reversing counter 2 (the symbol CT2 denotes the contents of the reversing counter 2), At the moment of time

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t | j in the reversible counter 2 is some negative number (GST2 and c diagrams), so after the arrival of each output impulse, the forwarder (24 signal of the signal of the reversible counter 2 decreases (time points to, t, t in the diagrams f, d, CT2i). At time t, the content of the reversible counter 2 becomes zero, and,, (diagrams f, GST2, b, d, e, Fig. 2) .This causes the next input pulse to invert the sign of the contents of the reversible counter 2 (diagram c at time tj, fig 2) and increases the content Reversing counter 2 (time t, on CT2 diagrams, figs, 2), Each subsequent input pulse of reversing counter 2 increases its contents (times t, t5, tg on f, d, GST2 diagrams, fig , 2)

The increase in the content of the reversible counter 2 is possible up to the maximum value, since the arrival of the next summing pulse will result in the contents of the lower bits being obiulit, and in the high (n + 1) -th digit there will be a transfer indicating the overflow of the discharge grid (time interval t on the charts f, CT2, g, fig, 2).

The time diagrams of the subtraction process in the reversible counter 2 () are shown in FIG. 3. These processes are in many ways similar to the summation processes considered (taking into account the fact that at time tp there is a positive number in the reversing counter 2), the difference is in the time dependence the sign of the content of the reversing estimator 2 (diagram with in FIG. 3). For reliable operation of the reversing counter 2, the counting pulses must be sufficiently short (their duration must be less than the total delay in the reversing the counter 2, the element OR-NOT 6, the decoder 18 and the first (or second) element IS-NOT 19), the function of shortening the counting pulses of the reversible counter 2 (if necessary) is performed by the driver 24 of the signal. The duration of the output pulses in the signal former 24 is determined by the RC time constant, which makes it possible to establish the necessary parameters.

meters of output pulses that can appear only with a single signal at the second input 26 of the device mode setting.

With a zero signal at the second input 26, the setting of the device mode does not pass the counting pulses to the input of the reversible counter 2, which allows the storage of the results (Stop mode) with a zero signal at the first input 17 of the setting of the device mode. In this mode, the contents of the reversible counter 2 does not change, which allows, after changing the values of parameters of some operating units (as part of an analog-digital computing system), to continue integration (solving the problem).

 In a reversible counter 2, a code is formed that is proportional to the integral of the product of two signals, one of which is represented by an analog form and is fed to the analog information input 15 of the device (U) and the other signal is a digital form. The input digital signal of the device is represented by a direct (n + 1) -disk code, the most significant bit of which is sign and is fed to the device via the sign input 16 of the device. The remaining bits represent the mantissa and are fed into the device via digital information input 27 of the device, which is connected to the digital input of the second digital-to-analog converter 4. The element EXCLUDE IT OR 5 processes the characters of the input analog signal (formed on the sign output of the converter 1 voltage to frequency) and digital signal. If the input digital signal is positive, then its sign signal is zero. At the same time, the EXCLUSIVE OR 5 element transmits the sign signal of the voltage converter 1 to the frequency without change. Otherwise, the sign signal of the voltage-to-frequency converter 1 is inverted.

Claims (1)

Formula image shadow An analog-to-digital integrating device containing a voltage-to-frequency converter, the clock input of which is the clock input of the device, and the information input is connected to the output of the digitizing multiplier five 0 5 0 r 0 W 0 five 066 Analogue converter, whose inputs are analog and digital information inputs of the device, respectively, the sign output of the voltage to frequency converter is connected to the first input of the element EXCLUSIVE OR, the second input of which is connected to the sign input of the device, a reversible counter, the installation input of which is connected to the digital input The initial conditions of the device, the lower output bits of the reversible counter, are the digital output of the device and are connected to the input of the OR-NOT element and The digital input of the digital to analog converter of which the output is an analog output device (n + 1) th output bit of the reverse. the counter is connected to the control output of the device, and the mode control input is the first input of the device mode setting, a trigger, the synchronization input of which is connected to the output of the AND element, the direct trigger output is a sign device output, characterized in that extending the functionality by implementing a result storage mode, a descrambler, five NAND elements and a pulse shaper are entered into the device, the output of the ICS element) CHA1 YATsEE OR connected to the first input m of the decoder, the second input of which is connected to the output of the element OR NOT, and the third input is connected to the forward output of the trigger connected to the sign input of the digital-to-analog converter, the information output of the voltage converter - the frequency is connected to the information input of the pulse shaper, whose resolution input is the second input of the device mode setting, and the output is connected to the counting input of the reversible counter and the first input of the AND element, the second input of which is connected to the output of the first NAND element, inputs connected to the even outputs of the decoder, the odd outputs of which are connected to the second element NOT-NOT, the output connected to the sign input of the reversible counter, the sign input of the initial conditions of the device connected to the first input of the third element AND-NOT and through the fourth element AND-NOT to the first input n to- 71376106 NAND element, the second inputs of the third and fifth NAND elements are connected to the first input of the device mode setting, the outputs of the third and fifth The elements of the NAND are connected to the installation input and the trigger reset input, respectively, the information input of which is connected to its inverse output. n n n n 0U & Z l l sriel