SU1488968A1 - Residue-class-system-code-to-positional-code converter with error detection - Google Patents

Description

The invention relates to computing and can be used in digital converters of computing systems. The aim of the invention is to reduce hardware costs. This goal is achieved by the fact that the device containing a group of blocks 2-7 elements And, the annular shift register 8, the element And 10, block 11 memory, block 12 multiplication, the adder 14 modulo 15 circuit comparison with a constant trigger 16 and the element OR 18, contains the shift register 9 and the shaper 13 module values with the corresponding connections. 1 il. 1 tab.

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The invention relates to computing and can be used in digital converters of computing systems,

The aim of the invention is to reduce hardware costs.

The drawing shows a diagram of a device for converting numbers from a code of a system of residual classes to a position code with error control.

The device contains a group of information inputs 1 device, a group of blocks 2 - 1 elements And, the ring register 8 shift, register 9 shift, element 10, block 11 memory, block 12 multiplication, shaper 13 module values, modulator 14, comparison circuit 15 with a constant trigger 16, the clock input device 17, the element OR 18, the device start input 19.

Combining the outputs of blocks 2-7 elements AND performs the function of logical OR.

The shaper 13 module values according to the module number, arriving at its input, generates the module value at the output and can be implemented as a ROM or a combination unit.

Block 11 memory can be implemented. on the ROM and has in the particular case of the encoding presented in the table.

In i AT 2 in _n ^In "4 AT 5 0 ^In 2, in _gz at 24 0 at 26 ⁱⁿ ZA, AT 2 0 in _? "four, B 42 0 at ₄₄ ^B 45 B ₄ b AT?, 0 in 53 ^In 54 B ₅₅ B 56 0 Ββ2 In <} 4 ^In 65 ⁱⁿ 66 ———

The comparison circuit 15 performs a comparison with a range value.

The invention is based on the projection method. It is known that in the presence of two redundant bases in the code of JUICE it becomes possible to correct a single error superimposed on the code word JUICE. For example, a JUICE has 4 workers and 2 control bases, then the working range is P _o = P, Ρ Ρ ₂ · P, · P ₄ , and the full P <o ⁼ P _o ^ 6 '. Thus, the number in the JUICE is represented as A =

^Ε (®I »Z.4» H5, ^a b) ·

If the code number of the RNS came without error, all projections of the number A will be equal to the number A, i.e. A =

⁼ (a, aI, a ₃ , a ₄ , a ^, a ^) ⁼ (a, a ₂ ,

a ₄ , a§) ⁼ (a ,, a ₂ , a ₃ , a ^, a ^) ⁼ = (a ,, a ₂ , a _e , a ₄ , a ₆ ) = (a _(a , a ₄ , a ₄ ,

a ₆ ) = (a ,, a ₃ , a ₄ , a ^, a ^) ⁼ (a ^, a ^, ^a 4> ^a 5> ^a &) ·

To translate the projections of the number A into the MSS, the expression

A = (a, 'B1d + a _g · B, _<g + a _} B | .5 + a ₄ B,. ₄ + a ₅ B ₁₅ ) to χιηοάΡ ,, Ρ, = Р, · Ρ _α · ₃ · .Ρ ₄ ·

similarly for other projections: P ₂ ,

"P4" P ₅ "

If a single error is superimposed on the code word SOK, then only one of the projections of the number will be equal to the number A, and the rest will not correspond to the range (0, P _o ).

The device works as follows.

At the initial moment of time, the code word SOK is set at the inputs 1 of the device. Blocks 2 - 7 elements And and element 10 are in the closed state, shift registers 8 and 9 and trigger 16 are in the zero state, in block 11 of the memory all possible bases (table) are recorded.

With the arrival of the trigger pulse, the trigger 16 is transferred to the single state. On the information inputs of the registers 8 and 9 shift arrives "1" (start signal). On the clock input of the register. 9 shift through the element OR 18 enters "1", ana clock input of the shift register 8 "1" comes from the input 1 7 of the device through the element 16 open by the trigger 16. which means the address of the orthogonal basis B _n located in the first column and the first line of the block 11 of memory. The output sequence of the shift register 9 also controls the shaper 13 module values, and the adder 14 is ready to sum modulo P,. Register 8 shift opens the block 2 elements And from the output of the element And 10 receives a signal to read from block 11 of the memory values In ,,. Thus, at the input of block 12 multiplication come 'a ₁ and b _and . From its input, the product enters adder 14 and is written to its res 1488968

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gistr. After that, from the device input 17, the second pulse arrives at the clock input of the shift register 8, and the sequence “000010” is formed at its output, which opens the block of 3 elements AND and changes the address of the column of the memory block 11. Therefore, the sum a ^ B ,, + a4B, _g , etc. With the arrival of the device of the sixth clock pulse from the output 17 of the output of the adder 14 to the input of the comparison circuit 15 with the constant, the first projection of the number A.

If A is p ₀ , then an error signal corresponding to the logical "1" from one of the outputs of the comparison circuit 15 will go to the clock input of the shift register 9, the output sequence of which changes the row address of the memory block 11 and sends a control signal to the driver 13, which rebuilds adder 14 for modulo summation, the circular shift register 8 will return to the state “000001” and the device will start calculating the second projection of the number A.

If the projection of the number A is έ p ₀ , then "1" from another output of the comparison circuit 15 with a constant will flip the trigger 16 and the shift registers 8 and 9 to the zero state and the conversion of the number A from the SOC to MSS will end.

Claims (1)

Claim A device for converting numbers from the code of the system of residual classes to a position code with error control, containing a group of blocks of elements AND, a ring shift register, an element AND, a memory block, a multiplication unit, an adder modulo, a comparison circuit with a constant, a trigger and an OR element, information inputs of the device group are connected to the first inputs of the corresponding blocks elements And, the second inputs of which are connected to the outputs of the corresponding bits of the ring shift register, _{with a} clock input which is connected to the output And, the first and second inputs of which are connected respectively to the clock input of the device and to the trigger output, the output of the memory block is connected to the input of the first multiplier of the multiplication block, characterized in that, in order to reduce hardware costs, it contains the shift register and driver 15 values of the module, with the outputs of the digits of the ring shift register connected to the inputs of the corresponding bits of the first address input of the memory block, the read resolution input which is connected to the output of the And element, the outputs of the bits of the shift register connected to the inputs of the corresponding bits of the second address input of the memory block and with the corresponding entrances 25 setting the module number of the shaper unit of the module, the output of which is connected to the input of setting the value of the modulo modulator module, the input of the addend of which is connected to the output of the multiplication unit the multiplier of which is connected to the combined outputs of the blocks of elements AND of the group, the device start input is connected to the installation input at "1" 35 trigger with information inputs ring shift register and shift register, with the first input element OR, the output of which is connected to the clock input shift register, output 40 modulo adder connected to the input of the comparison circuit with a constant, the output of "More" which is connected to the second input of the OR element, the output "Less than or equal to" the comparison circuit with constantoy connected to the installation input to the "0" trigger and the reset inputs of the ring register shift and shift register.