SU1501030A1 - Series to parallel code converter - Google Patents

Abstract

The invention relates to computing and can be used to convert a serial binary sign bit code into a parallel binary additional code. The purpose of the invention is to simplify the device. The device contains an element 1, a converter 2 codes, an arithmetic unit 3, registers 4, 5 memory, information inputs 6, 7, clock inputs 8, 9 and outputs 10. 2 Il, 2 tab.

Description

fff

CAD

150

The invention corresponds to the numerical technique and can be transformed into an arithmetic device for converting an item. hessha-tel1, a binary binary zlkoratrar jmch) move to a parallel double additional code.

The aim of the invention is to simplify the device.

FIG. 1 shows a functional diagram of the device; FIG. 2 shows timing diagrams of his work.

The device contains element I 1, code converter 2, (n + 1) -arithmetically block 3, first and second registers 4 and 5 of memory, first and second information inputs 6 and

7, first n second clock inputs

8.9., And (n + 1) bit outputs 10 of the device.

In binary binary code, an n-bit number C is represented as:

WITH

(t

C ;, C e

T. o, 1,

where I means - 1.

The number C comes to the first, second information inputs of the device with the most significant bits ahead, and the first information input 6 of the device receives the positive part of the number C, and the second information input 7 receives the negative portion of the number C, as shown in Table. one.

The principle of operation of the device is as follows.

When entering the information inputs 6 and 7 of the device for the sign of the beginning of a number in the first and second (lower) bits of register 4, zeros are written. When the digit 1 arrives, block 3 performs the operation of summing the numbers arriving at its inputs. If both of its inputs have a single number, this is equivalent to shifting this number by one bit toward the higher bits. Then, the unit is subtracted from the resulting number. When the number 1 arrives, the number is shifted and the unit is added to it in the same way; Upon receipt of the sign of the beginning of the next number, the result of the transformation is written

thirty

to register 5 and the conversion of the number in the next number begins.

Consider the operation of the device for converting from a serial binary sign-digit code into a parallel binary additional code when converting the number C 1 O 1 (p 3). .

0 Converter code 2 generates the code of the operation mode of the unit 3 in accordance with the table. 2

Suppose that in the initial state all bits of register 4 are in the single state.

On the decline of the first clock pulse arriving at the clock input device 9, to the information inputs 6 and 7 of the device simultaneously

0 units are the sign of the beginning of a number. In this case, the converter 2 sets the mode (A + B) of block 3, which actually means a shift of the contents of register 4 to the direction of the higher bits, and the output of block 3 will be zero at the first discharge of block 3. On the front of the first clock pulse coming from the clock input 8 of the device, a shifted number is recorded. Then, a unit is set at the clock input 9 of the device, block 3 is again in the mode (A + B) and on the front of the second clock pulse coming from the clock input

5 of the device, the contents of register 4 are again shifted towards the higher bits, with zero being written to its first bit.

From the decay of the second clock pulse arriving at the device clock input 9, the information inputs 6 and 7 of the device receive, respectively, zero and one — the first (senior) bit of the input number C, equal to i. On the front of the third clock pulse coming from the clock input 8 of the device, the number in register 4 is again shifted as described. When a unit arrives at the device clock input 9, the converter 2 switches the block 4 to the mode (A-1) ,. and on the front of the fourth clock pulse coming from the clock input 8 of the device, the result is written to register 4.

five

The decline of the third clock pulse arriving at the clock input 9 of the device, the information inputs 6 and 7 of the device arrive

five

the zeros are the second ra: sp and the current of the number C, equal to 0. The number is shifted again. in register 4, as described. Then, when units are received at the device clock input 9, the converter 2 converts the block 3 to mode A, i.e. the number in registers 4 does not change. .

As the fourth clock pulse arrives at the device clock input 9, the information inputs 6 and 7 of the device receive one and zero, respectively — the third bit of the input number C. equal to 1. The number in register 4 is shifted again, then its content is subtracted unit.

After the decline, of the fifth clock pulse that arrives at the clock input 9 of the device, the information inputs 6 and 7 of the device again receive units — a sign of the beginning of the next number. In this case, the signal at the output of the And 1 element corresponds to the TaKTOBONty input 9 of the device, and on its front, the result of the conversion from register 4 to register 5 is recorded and the next number is converted.

The most significant bit of the device outputs 10 is significant. Result

m

1 lit) 1030

| rheG) 1)) and ghchppspt

His status) 1G G-PST). i

F

about r m

h t f) p

t o and h

Ustr (111stguyu for the probable. Consequences of the last tl-l pto cat p tralpol nl code containing the third register, th-m; - this input is the third clock input of the device, nyhol are connected to the alternate 1 and the second inputs The element I, the first, second and third inputs of which are respectively the first, second information and second clock inputs of the device, the output of the AND element is connected to the clock input of the second register, the outputs of which are the outputs of the device, characterized in that to simplify the arithmetic unit and the code converter, the first, second and third inputs and outputs of which are connected respectively to the first, second information and second clock inputs of the device and the control of the same name, and the inputs of the arithmetic unit, information inputs and outputs of which are connected to the same-name outputs and the same-name information inputs of the pair-register.

Table 1

Note. A & B-numbers do

respectively, the first and second inputs of block 3, X is an arbitrary state.

FIG. 2

Claims (1)

Form y. I don’t need to read <> t hi ro gn.st. and i take A device for converting a serial cat into a parallel code containing a first register, the clock input of which is the first clock input of the device, the outputs are connected to the same information inputs of the second register, the element And, the first, second and third inputs of which are the first, second information and second clock, respectively the inputs of the device, the output of the And element is connected to the clock input of the second register, the outputs of which are the outputs of the device, characterized in that, in order to simplify the device two, the arithmetic unit and the code converter are entered into it, the first, second and third inputs and outputs of which are connected respectively to the first, second information and second clock inputs of the device and the control inputs of the same name of the arithmetic unit, the information inputs and outputs of which are connected respectively is iconic. The result is the same as the outputs of the same name with the information inputs of the first register.