SU1129732A1 - Delta modulator - Google Patents

Abstract

DELTA-MADAFLTOR5 containing sequentially connected comparator, delay trigger and shift register, the forward and inverse outputs of the bits of which are connected to the inputs of two corresponding groups consisting of elements connected in series, a polarity converter, a digital-to-analog converter, two keys an inverter and an integrator , the output of which is connected to the calculating input of the comparator, the summing input of which is connected to the input bus, the direct output of the delay trigger is connected to the output bus, and the clock inputs trigger delay and shift register are connected to the clock bus, which is distinguished with the fact that, in order to increase the signal-to-noise ratio, two groups of elements SH, group of successive registers, RS-trigger and adder are introduced, and the inputs of each IL element of the first group are connected with the outputs of the corresponding elements of the first and second groups, the outputs of the elements OR of the first group are connected to the inputs of the corresponding successive registers, the direct outputs of the bits of which are connected to the inputs of the corresponding elements OR of the second group, the outputs of which are connected to the inputs of a digital-to-analog converter, the output of which is connected to the input of the first key and through the inverter to the input of the second key, the outputs of the first and second keys are connected to the corresponding inputs of the cooler, whose input is connected to the input of the integrator. RS-flip-flops are connected to the corresponding inputs of the first element OR of the first H from the group, and the direct and inverse outputs are connected to the control of the flip-flop inputs of the first and second keys, respectively, OE, in addition, the inputs w ers polarity are connected to the direct and inverse outputs of the delay flip-flop, and an output connected to a further input of the adder and serial clock inputs of registers connected to the clock bus.

Description

The invention relates to a pulse technique and can be used in digital lines of information transmission. A delta modulator with inertial companding is known, which contains a pulse shaper and a shift register, two AND elements, an OR element connected in series, a smoothing filter, a constant offset adder, an amplitude-pulse modulator, and the TI J integrator. -modulator is a low signal-to-noise ratio. The closest technical solution to the proposed is a delta modulator containing a serially connected comparator, a delay trigger and a shift register, the forward and inverse outputs of the bits of which are connected to the inputs of two corresponding groups consisting of the elements connected in series And the polarity converter digital-to-analog converter, two keys, an inverter and an integrator, the output of which is connected to the subtractive input of a comparator, a summing input. Which is connected to the input bus, direct output is a trigger and Ser nen delay to the output bus and the clock inputs of the flip-flop and a delay shift register connected to the bus clock, and also comprising a logic circuit consisting of a JK-flip-flops, inverter for ditch and the AND 2. A disadvantage of the known devices is also the low signal-to-noise ratio. The purpose of the invention is to increase the signal to noise ratio. This goal is achieved by the fact that, in a delta modulator containing a serially connected comparator, a delay trigger and a shift register, the forward and inverse outputs of the bits of which are connected to the inputs of two respective groups consisting of elements connected in series AND, the field converter digital converter converter, two keys, an inverter and an integrator, the output of which is connected to the subtractive input of the comparator, the summation of the input of which is connected 22 to the input bus, the forward output of the trigger trigger is connected with the output bus, and the clock inputs of the delay trigger and the shift register are connected to the clock bus, two groups of OR elements are introduced, a group of consecutive registers, an RS trigger and an adder, the inputs of each RSHI element of the first group are connected to the outputs of the corresponding elements of the first and second groups , the outputs of the OR elements of the first group are connected to the inputs of the corresponding successive registers, the direct outputs of the bits of each of which are connected to the inputs of the corresponding OR elements of the second group, the outputs of which dinene with inputs of a diffraction analog converter, the output of which is connected to the input of the first key and through an inverter to the input of the second key, outputs of the first and second keys are connected to the corresponding inputs of the transmitter, the output of which is connected to the corresponding RS-flip-flop; by their inputs of the first element OR of the first group, and the direct and inverse outputs, with the control inputs of the first and second keys, respectively, in addition, the inputs of the polarity converter are connected to the direct and inverse odes delay flip-flop, and an output connected to a further input of the adder and serial clock inputs of registers connected to the clock bus. Figure 1 presents the block diagram of the device i figure 2 - timing charts of its work. The device contains a comparator 1, a trigger 2 delay, a shift register 3, the first and second groups 4 and two-input elements 6 I, the first group of elements 7 OR, the group of consecutive registers 8, the second group of elements 9 IL, the digital-analog converter 10, the inverter 11, the first and the second keys 12 and 13, the adder 14, the integrator 15, the RS-trigger 16, the polarity converter 17, the input bus 18, the output bus 19, the clock bus 20. The output of the comparator 1 is connected to the trigger input 2 of the delay, the direct output of which is connected to the input of the register 3 shift and to the output bus 1 9. The direct outputs of bits 3 of register 3 are connected to the inputs of the first group 4, and the inverse outputs to the inputs of the second group 5, each of these groups consists of two-input elements 6 I connected in series. The outputs of the same order of elements 6 of both groups 4 and 5 are connected to the inputs of the corresponding elements 7 OR of the first group, the outputs of which are connected to the inputs of the successive registers 8. The bits of the bits of each register 8 are connected to the inputs of the corresponding element 9 OR of the second group. The outputs of the elements 9 OR connected to the inputs of the digital-to-analog converter 10, the output of which is connected to the input tag; the inverter 11 and the first key 12. The input of the second key 13 is connected to the output of the inverter 11. The outputs of both keys 12 and 13 are connected to the inputs of the adder 14, to the auxiliary input of which the output of the converter is connected: I 17 polarity. The output of the adder 14 is connected to the input of the integrator 15, the output of which is connected to the subtractive input of the comparator 1, the total input of which is connected to the input bus 18. The outputs of the delay trigger 2 are connected to the inputs of the polarity converter 17. The inputs of the RS-flip-flop 16 are connected to the inputs of the first element 7 OR of the first group. The direct and inverse outputs of the RS-flip-flop 16 are connected to the control inputs of the first and second keys 12 and 13, respectively. The clock bus 20 is connected to the clock inputs of the trigger 2 and registers 3 and 8. The first consecutive register 8 has as many bits as there are 7 elements of the RIGA in the first group, or one bit less than the register. 3 shifts. Each subsequent register 8 has one bit more than the previous one. In figure 2, the following is indicated: U (t) to the input signal Yt - signal on the output bus 19 of the delta modulator of the torus fc - clock pulses x (t)., XjCt), Xj (t) - shortened by one, two and three delta symbols -modulated (dm) signal Y (t) at the outputs of elements 7 OR; Z;, (t), ZjCt), Zj (t) - signals formed from signals x (t), xj (t), Xj (t) at the outputs of elements 9 OR in those cases x 324 when in DM signal V ( t) there are packs of ones or zeros; (t) the signal at the output of the digital-to-analog converter 10-, V (t) is the control signal for the quantization step at the output of the adder.14; 0 (t), & t (t) control signals from the outputs of the RS flip-flop 16, indicating, respectively, that the input signal U (t) increases or decreases, i.e. the presence of single or zero packs; Yf (t) signal at the output of the polarity converter 17; U (t) is the approximating voltage from the output of the integrator 15. The device operates as follows. Suppose that on bus 18 there is a sinusoidal input signal U (t). As a result of the comparison, in the comparator 1 of the input U (t) and the approximating U (t) voltage, its output produces a single or zero voltage level, which, upon arrival of the clock pulse, is written to the trigger 2 delay and stored for one clock cycle. As a result, the DM signal Y (t) is formed at the output of the trigger 2 delay. G Figure 1 shows a four-bit shift register 3. Depending on the number of symbols in the DM bursts of the Y signal (t) at the outputs of elements 6, the packs are shortened by 1, 2, and 3 symbols, and alternate pausing combinations of 1.0, 1.0 characteristic for idling are also excluded. As a result, the outputs of elements 7 OR of the first group receive signals x (t),), XjCt) of different duration and with different weights. The x.j (t) signal indicates the need for a larger increase in the quantization step than the signal), XjCt) —more than x (t). Further, from the signals x (t), Xj (t), XgCt), form the signals using successive registers 8 and elements 9 OR of the second group, auxiliary control signals of the quantization step z (t), z (t), Zj (t) according to this law: The signal z (t) must be present at all time intervals, while in the DM signal Y (t) there are packs with the number of characters. The signal zj (t) must be present at all time intervals, while in the DM Y (t) there are packs with the number of symbols n / 3, 5 signal Zj (t) - with packs with pe 4. If you want to expand the dynamic range of the input speech signals or increase the signal-to-noise ratio, then the same principle can form signals x (t), x (t), etc. From the auxiliary signals z (t), ZjCt) and Zg (t), using a digital-to-analog converter 10, a multi-level signal V (t) is formed, and its maximum values are smoothed in time in those places where the DM signal packs those. where the speed of the input analog signal U (t) is maximum. The signal (.t) is inverted and then fed directly to keys 12 and 13 in direct and inverse form. For single bursts, the signal (t) is switched to the input of adder 14, and the signal inverse (t) is at zero signals. The adder 14 also receives the DM signal Y (t), which, after the polarity converter 17, is formed as a signal consisting of single packs represented by level + E and zero packs represented by level -E. Thus, even in the absence of signals 6. From the outputs of keys 12 and 13, the delta modulator will operate in a linear mode, since the signal Y (-t | is always present at the input of the adder 14. As the input signal U (t) increases, the voltage level of the signal {-fc) increases, and, therefore, the signal V (t), which eliminates the overload of the delta modulator and increases and stabilizes the signal-to-noise ratio over the entire dynamic range of the input signal. As is known from theory, the adaptation of a delta modulator to the input signal is best, i.e. the signal-to-noise ratio is maximum if the ratio U, / V is constant when the input signal U (t) changes. Thus, as a result of more accurate tracking of the input signal in the proposed delta modulator, the signal-to-noise ratio is increased. In addition, the possibility of an integral implementation of the proposed delta modulator appears. In this case, the integrator is eliminated, and the loss in the signal-to-noise ratio is compensated for by increasing the discrete part (the number of auxiliary signals xKt), z;. (T).

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Claims (1)

DELTA-MODULATOR, containing a comparator connected in series, a delay trigger and a shift register, the direct and inverse outputs of the bits of which are connected to the inputs of two corresponding groups consisting of AND elements connected in series, a polarity converter, a digital-to-analog converter, two keys, an inverter and an integrator, the output of which connected to the subtractor input of the comparator, the summing input of which is connected to the input bus, the direct output of the delay trigger is connected to the output bus, and the clock inputs of the trigger delays and shift registers are connected to the clock bus, characterized in that, in order to increase the signal-to-noise ratio, two groups of OR elements, a group of consecutive registers, an RS-trigger and an adder are introduced into it, and the inputs of each OR element of the first group are connected to the outputs of the corresponding elements AND of the first and second groups, the outputs of the OR elements of the first group are connected to the inputs of the corresponding sequential registers, the direct outputs of the bits of each of which are connected to the inputs of the corresponding elements OR of the second group s, the outputs of which are connected to the inputs of the digital-to-analog converter, the output of which is connected to the input of the first key and through the inverter to the input of the second key, the outputs of the first and second keys are connected to the corresponding inputs of the adder, the output is connected to the input of the integrator, while the RS inputs -trigger are connected to the corresponding inputs of the first element OR of the first group, and the direct and inverse outputs are connected to the control inputs of the first and second keys, respectively, in addition, the inputs of the polarity converter are connected to direct the output and inverse outputs of the delay trigger, and the output is connected to an additional ⁴ additional input of the adder, and the clock inputs of the serial registers are connected to the clock bus.