SU1215168A1 - Digital accumulator of pulsed signals - Google Patents

Abstract

The invention relates to a pulse technique and can be used in various digital measuring complexes for repetitive pulse signals from a mixture of noise and other interference. Purpose and invention - improving speed: VIA. Device contains analog W

Description

digital converter 1 with output signal 20, block 2 of the memory of input signals with signals 21 22 at its outputs, shift register 3, bus 4 logical 1 with signal 23,. two-input adders 5 and 6 with signals 24 and 25 at their outputs, a generator of 7 clock pulses with a signal 17 at its output, a delay element 8 with an output signal 18, a block 9 comparing with a threshold, register

 The invention relates to a pulse technique, in particular to devices for converting a series of pulsed signals, and can be used in various digital measurement systems to separate repetitive pulse signals from a mixture of noise and other interference.

The aim of the invention is to increase speed.

Figure 1 shows the functional diagram of the digital storage device; 2 shows timing diagrams for his work.

Digital storage of pulse signals contains analog-to-digital converter 1, block 2 of the memory of input signals, 3 shift registers, 4 bus logical 1, two-input adders 5 and 6, clock generator 7, delay element 8, comparison block 9, for example, digital comparator, block 10 of memory of output signals, shift registers 11, block 12 of initial setup, resistor 13, capacitor 14, inverter 15.

In Figure 2, the following notation is entered: 16 is the signal at the output of the setup unit; 17 - clock sequence or generator output 7 clock "mp; 18 is a clock sequence at the output., The delay element 8; 19 - signal to the drive; 20 - signal at the output of the analog-digital converter; 21 - signal at the first output, J 2 block of the input signals memory 22 - signal at the second output of the block 11 of the memory block 10 of the output signals 26 and 27, block 12 of the initial setup with a signal 16 at its output, resistor 13, capacitor 14 and Inverter 15. A signal 19 is output to the information input of the analog-digital converter 1, which is the drive input. The output signal of the storage device is 28. The description shows time diagrams for the storage device. 2 Il.

ka 2 memory input signals; 23 - the signal on the bus 4 logical 1, 24 - the signal at the output of the adder 5; 25 is a signal at the output of the adder 6; 26 is a signal in the first bits of the shift register 11 of block 10; 26 is a signal at the output of the block 10 of the memory of output signals; 28 - drive output signal.

The information input of the analog-digital converter 1 is the input of the accumulator, its clock input is connected to the generator output 7 clock pulses and to the input of the element 8

delays, and the output - with the information input of the block 2 of the memory of input signals. The 3 shift registers of block 2 of memory each have N Mx n + 1 bits each (M is the number of channels, n is the number of accumulated pulses). The total number of shift registers 3 is m and the half-width of the analog-digital converter I. The clock inputs of the shift registers 3 are combined and connected to the output of delay element 8. The inputs of the initial installation of the register 3 shift combined and connected to the output of the block 12 of the initial installation.

The first output of block 2 of the input signals, formed by direct outputs of the first bits of shift registers 3, and the second output of block 2, formed by inverse outputs of the last bits of shift registers 3, are connected respectively to the first and second inputs (inputs of the first and second operands) adder 5. Input transfer to the younger bits adder i

5 is combined with (t + 1) -th (.ignal bit of the second operand and connected to bus 4 logical 1, and (t + 1) -th (significant) bit of the first operand connected to zero bus. Such switching on the adder 5 provides using it as a subtracting block when the first operand is a positive number and the second operand is a negative number. The output of the adder 5 is connected bitwise (from the 1st to (ha + 1)) and the first input f -discharge adder 6. In the adder 6, the leading bits of the first operand, starting with (t + 1) -th bit, are combined, and the input is transferred This bit is naturally (directly from the binary arithmetic rule) when summing two operands, the first of which is alternating and has a smaller bit size than the second (i.e., the first term is smaller in absolute value). the second operand is always positive. The second input of the adder is connected one bit to the output of the output memory block 10 formed by the direct outputs of the last bits of the shift registers 11, and the output to the information input of the block 10 and to the first input of block 9 of comparison with the threshold. The shift registers 11 of the memory block 10 of the output signals each have M bits, and their total number is f and is equal to the bit of the adder 6. The clock inputs of the shift registers 11 are combined and connected to the output of the delay element 8. The inputs of the initial installation of the shift registers 11 are combined and connected to the output of the initial installation block 12. In the latter, the resistor 13 and the capacitor 14 are connected in series between the bus 4 of logic 1 and the zero bus, forming a timing circuit to which the output inverter 15 is connected. The bits of the second input of the comparison unit 9 are connected to the bus 4 of logical 1 and to the zero bus in accordance with required threshold value. The output of comparison unit 9 is the output of the accumulator.

This device performs the accumulation of pulse signals in one (rm) channel (range element and

 5168

The following comparison of the accumulated signal with the threshold in accordance with the rule of accumulation on a sliding interval

5i-1

M

V (V

CD

ten

where n is the number of accumulated pulses (the width of the sliding interval); X - quantized in amplitude

and time values of the input

(P

signal delayed by r cycles;

y - amplitude-quantized

and the time value of the output signal;

с - digital threshold.

To clarify the principle of operation of the accumulator, we apply the rule of accumulation on a sliding interval in the zth channel. We write the expression or k-ro and (k-l) -ro periods of work:

V.-1

,, (“) Sr () +

CC ".-AND --- K-h + t K.-h-ft-.

  - ° (g)

I

, -.,). y -), (. 1 -x - - x)

30, YK-I 2.-1- (k-1. -G K-hH-i; -hСЗ)

Subtract from

(h

K-1

t.) from y and carry

u in the right-hand side, we obtain after the relegation of similar members the recurrent rule of operation of the accumulator in rm

channel

t) (

KM

+ -Y

d)

to (4)

The principle of operation of the accumulator in accordance with the expression) is illustrated by the example of its operation with specific values of the number of channels and the number of accumulated pulses.

. The given example also corresponds to timing diagrams in FG.2, and on the time diagrams the values of signals on all information-HfK digital multi-digit inputs and outputs (binary multi-digit numbers) are represented conditionally in the form of pulses with an amplitude proportional to the magnitude of the corresponding signals. For definiteness, the time diagrams are given for the case when a signal corresponding to the presence of three pulses in the first and third channels acts at the input of the accumulator, with the amplitudes of the pulses in each of the channels being respectively three and one conventional unit.

After turning on the power, the drive automatically returns to its original position, in which the shift registers 3 and 11 of the blocks 2 and 10 of the memory are reset to zero states. The reset signal is generated by block 12 of the initial setup as follows.

The capacitor 14 of the block 12 to the power supply discharge. When the power is turned on, the voltage on the capacitor does not change abruptly, so the input level of the inverter 15 is logic level O, and the output voltage is logic level 1. As the capacitor 14 charges through the resistor 13, the voltage across the capacitor increases and after a time determined by the constant charging time, the time — the driving circuit — reaches the level at which the inverter goes from one to zero. As a result, a positive impulse (16 per fng, 2) is formed at the output of the initial installation unit 12, which enters the initial installation of the shift registers 3 and 11 and sets them to the zero state.

The input signal (1 9 in Fig. 2 arrives at the informational in:. Analog-digital converter 1, the clock input of which receives pulses from the generator output 7 clock pulses (1 7 in Fig. 2) s.

ode, equal duration of accumulated impulses. The signal quantized in amplitude and time .20 of FIG. 2), represented by the binary wi-bit code, from the output of the analog-digital converter I is fed into the 3 shift registers of the block 2 of the memory of input signals, to the clock inputs of which output 8 delay, a sequence of shift pulses (18

T T in figure 2) with a period T.e -: j T

determining the processing time of a single channel (.T is the period of the following input pulses in each of the channels). Samples of the input signal, related to adjacent channels, turns out

There are always in the adjacent bits of the 3 shift registers and are consistently advanced in them. Since the number of bits of the shift registers 3 is N M "n + 1 13, the information on the input signal is stored in n (three) previous periods of all M (four) channels and the next value of the processed channel.

As can be seen from the above, in the first and last bits of the 3 shift registers there is information relating to the same channel processed in a given clock cycle, and in the first bits this is xi, and in the last times I b / l I

Indicated

r dah -, x D

j

five

0

five

the input signal values are fed simultaneously to the adder 5, with xj being in the forward code and in the return code (21 and 22 in Fig. 2, since x ,. is supplied from the inverse outputs of the last bits of the shift register 3. Reverse) the code of the number X together with the logical 1 signal supplied to the adder 5 from the bus 4 of the logical 1 (23 in FIG. 2) form an additional code of the number xU so that the output of the adder 5 has a number equal to the difference x1H - - C24- X c to-h

2). This number enters the adder 6, to the second input of which simultaneously feeds the previous value of the output accumulated signal of the processed channel Y, -Y. from the outputs of the last bits of the shift register registers 11 of the memory block 10 (27 in Fig. 2.) After summing up, the output of the adder 6 produces a positive number representing the accumulated value of the output

channel processing signal

(11 Uts, which enters the input

block 9 is compared with the threshold and to the inputs of registers 11 of block 10 of the memory of output signals. The value is compared with a threshold, the value of which in the form of a binary number is constantly acting on the second input of block 9 (25 in Fig. 2). When the output signal y is exceeded, the threshold at the output of the accumulator appears a pulse normalized in amplitude, which indicates the detection of the accumulated signal in this channel (28 in Fig. 2). Upon receipt of the next pulse shift numbers

(-eleven

The j of j is recorded in the first bits of the shift registers 11 of the memory block 10 (26 in Fig. 2), the next value of the input signal is written in the first bits of the shift registers 3 of the memory block 2, all information in the registers 3 and II is shifted by one bit, and the drive goes to the second channel processing. Exactly four clock cycles, i.e. after a time T equal to the pulse following period, when the drive again processes the first channel in (k + l) -M cycle, the number will appear in the last bits of the shift registers P, since the number of register bits 11 is equal to the number of channels.

In the process of accumulating n pulses in adjacent periods, the accumulated signal can be n times the input signal, so the number of numbers to represent it must be log n (the designation of the nearest integer number greater than or equal to the number of the input number to eliminate the possibility of overflowing the discharge grid. This is achieved by selecting the number of shift registers 1I equal to Г m J log г riT and the corresponding size of the adder 6.

Claims (1)

Invention Formula A digital storage of pulse signals containing an analog-to-digital converter, whose information input is a power input, a clock input is connected to the output of a clock generator, and the output is connected to an information input of an input signal memory block consisting of "shift registers with a combined clock inputs that form the clock input block, and  a comparison unit with a threshold, the output of which is the output of the storage device, y 15. 0 S:; about five 0 five 0 characterized in that, in order to monitor the speed, the first adder, the second adder, the initial setup block, the delay element and the memory block of the output signals, consisting of the P-discharge shift registers with the common clock inputs and the initial settings, forming respectively a clock input and a block setup initial input, where M is the number of channels, is the number of accumulated pulses, 3 is the nearest number greater than or equal to fog ih, while the shift registers of the input signal memory block are M x h 1 their inputs, and the initial inputs of the initial installation are combined and form the input of the initial installation of the block, and its first and second outputs, formed respectively by the direct and inverse outputs of the first and last bits of the shift registers, are connected respectively to the first and second inputs of the first adder, the input the transfer of the lower bit of which is connected to the bus logical 1, and the output to the first input of the second summator, the second input of which is connected to the output of the memory block of the output signals, formed by the direct outputs of the last bits in the shift registers of the block, its information input is connected to the input of the comparison block with the threshold and with the output of the second adder, the clock inputs of the memory blocks of the input and output signals are connected to the clock generator through the delay element, and the initial setup of the memory blocks of the input and output signals - to the output of the initial installation block, the input of which is connected to the bus of logic 1, and the bits of the threshold signal of the comparison block with the threshold are connected to the logic 1 n i-zero pin. fug. 2