SU1387199A1 - Pulse recurrence conversion device - Google Patents

Abstract

The invention relates to automation and converter technology and can be used in digital phase synchronization systems. The purpose of the invention is to increase the speed of forming the output pulse sequence. A digital pulse frequency conversion unit contains a group 1 of N + L serially connected counting triggers, a shaper of 2 pulses, an OR 3 element, a jV-bit register 4, a group of 5 of delay elements, a group of 6 of N gating elements and L + 1- bit adder 7. Introduction to the device of group 6 from / V gating elements, L + 1-bit adder 7, delay 2 shaper allows to increase the speed and reduce the delay time of forming the output pulse sequence when changing control Code to a value not exceeding the period of the pulse sequence of the converted sequence. 2 Il. (Q (L

Description

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with so

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FIG.

The invention relates to automation and converter technology and can be used in digital synchronization systems of communication stations.

The purpose of the invention is to increase the speed of forming the output pulse sequence.

FIG. I shows the functional diagram of the device; in fig. 2 - timing diagrams for the operation of the device.

The device for digital conversion of the pulse frequency contains a group of 1 of () serially connected counting triggers, the driver

The ditch through the / and open strobe element 6 is fed to the / -th inputs (+1) -space of the 1d adder 7, which provides the summation of codes of numbers modulo 2 (+1) depending on the value Y of the control code per The outputs (L + 1) -discharge adder 7 generate a time-varying code. FIG. 26-g shows the formation of codes at the outputs of the (L + 1) -discharge adder 7 for cases corresponding to the decimal equivalent of Zy of the control code 1, 2, .3, 4, 5, and 7, respectively.

Shaper 2 pulses produces standard pulses each time.

2 pulses, element OR 3, yV-bit. when the output signals (L + l) -ro bit register 4, the group 5 of the / V elements of the adder 7 is changed from the level "Log.O

holders, a group of 6 of the / V strobing elements and a (1 + 1) -discharge adder 7.

The device works as follows.

Upon receipt of the control pulse code on the input bus of the digital 20, the time interval is equal to the control period at the output of the element OR 3 pulse backing of the input pulse

The pulse signal is set, which sets the counting triggers 1 - 1 - I - (/ V + L) to one state and zeroes the L-discharge register 4. As a result, the elements 6-1-6-N strobe are blocked, In the inputs of which the signals "Log O are generated, arriving at the inputs of the (L - + - 1) -discharge adder 7. At the same time, at the output of the {L - {- + 1) -th bit of the adder 7, the signal" Log.O.

on "Log. 1 (Fig. 2 3-n). The delay in the formation of the first pulse of the output sequence relative to the time instant of the change of the control code does not exceed the sequence.

Claims (1)

Invention Formula 25 A pulse frequency conversion device containing a group of) serially connected counting flip-flops, the counting input of the first of which is the input information bus 30, the / V-bit register and the OR element, 35 characterized in that, in order to increase the speed of forming the output pulse sequence, a group of N gating elements is entered into it, (Lf-1) -digit adder with N inputs, a pulse shaper and a group of N delay elements whose inputs are combined with the corresponding the inputs of the OR element are the input bus of the digital control, the outputs of the delay elements of the group are connected to the corresponding information. After some time, specified by the 5-1-5-L delay elements, the VU-discharge register 4 is entered into a new Y of the control code, in accordance with which the corresponding gating elements of group 6 are opened. With the input of the counting trigger 1 - 1 of the first pulse of the input transformed sequence with the frequency / t of the pulse following (Fig. 2a) on the inverse outputs of all () counting flip-flops are formed by 40 L / -digit registration inputs — Log.I. Voltage levels “Log. 1 pa whose outputs are connected to the inputs through the corresponding open gating elements 6 of the corresponding gating elements are fed to the inputs of the (L + l) gating group, and the installation input is bit adder 7, at the output of (L + 1) -zero state is combined with the same bit of which is formed by the signal inputs () -x counting triggers “Log. 1. As a result of changing the direction of the group and connected to the output of the element OR. No output (L + l) -ro bit of adder 7 from the level "Log.O to" Log. 1 shaper 2 pulses at its output generates the first pulse of the output of the converted pulse sequence. Upon receipt at the input of group 1 of the counting triggers of successive pulses of the input sequence at the inverse outputs counting triggers, a linearly decreasing binary code is generated. Signals from inverse outputs from / -TH to () -H counting trigger-inverted outputs from the gth to () -n counting triggers of the group are connected to the corresponding information inputs of the / -th gating element of the group, outputs gp of each / -H gating element of the group are connected with the corresponding / th inputs () -digmator with N inputs, the output of the (L + 1) -th bit of which is connected to the input of the pulse former, the output of which is the output thickness, and 2, ..., L. The ditch through the / and open strobe element 6 is fed to the / -th inputs (+1) -space of the 1d adder 7, which provides the summation of codes of numbers modulo 2 (+1) depending on the value Y of the control code per The outputs (L + 1) -discharge adder 7 generate a time-varying code. FIG. 26-g shows the formation of codes at the outputs of the (L + 1) -discharge adder 7 for cases corresponding to the decimal equivalent of Zy of the control code 1, 2, .3, 4, 5, and 7, respectively. Shaper 2 pulses produces standard pulses each time.  when the output signals (L + l) -ro of the discharge of the adder 7 change from the level "Log.O when the output signals (L + l) -ro of the discharge of the adder 7 change from the level "Log.O spawns a time interval equal to the pulse following pulse input on "Log. 1 (Fig. 2 3-n). The delay in the formation of the first pulse of the output sequence relative to the time instant of the change of the control code does not exceed the sequence. Invention Formula A pulse frequency conversion device containing a group of) serially connected counting flip-flops, the counting input of the first of which is the input information bus, the / V-bit register and the OR element, characterized in that, in order to increase the speed of forming the output pulse sequence, a group of N gating elements is entered into it, (Lf-1) -digit adder with N inputs, a pulse shaper and a group of N delay elements whose inputs are combined with the corresponding the inputs of the OR element are the input line of the digital control, the outputs of the delay elements of the group are connected to the corresponding information inputs of the L / -size register, the outputs of which are connected to the gates of the corresponding gating elements of the group, and the installation input in group and connected to the output of the element OR. the inverse outputs from the rth through () -n counting trigger group are connected to the corresponding information inputs of the / -th gating element of the group; The output of (L + 1) -th bit of which is connected to the input of the pulse former, the output of which is the output thickness, and 2, ..., L. Illlllllllllllll Ill Illlllllllllliilllill Well I I I I I I I I I I I I I I I I I I