SU549801A1 - Device for converting binary to decimal code to binary - Google Patents

Description

I

The device relates to the field of computer technology and can be used in computers and devices where it is necessary to convert information from a binary decimal system to a binary one.

Devices are known for converting a binary-decimal code to binary 1, containing shift and memory registers for convertible binary-decimal code and its output binary equivalent, And elements and correction nodes. Such devices contain two multi-bit ones (registers, correction nodes by the number of tetrads in the convertible binary-decimal code, which complicates the device.

The closest technical solution to the problem is the converter of the correct binary-decimal fraction into binary 2, containing the distributor) of pulses, the delay register, the correction unit and the selection unit.

The circuit of such a converter is complicated.

The object of the invention is to improve the device.

This goal is achieved by the fact that a trigger and a number register are introduced into the proposed device for converting binary-binary code to DOUBLE-DIAL. The group of outputs of the number register is connected to the first group of inputs of the selection unit, the group of outputs is connected to the group of inputs of the correction unit, the group of outputs of which is connected to the delay register, the first, second and third outputs of which are connected respectively to the first,

the second and third inputs of the number register, and the fourth output of the delay register is connected to the fourth input of the number register and to the first trigger input, the output of which is connected to the fifth input of the number register. The first and second outputs of the pulse distributor are connected to the sixth and seventh inputs of the number register, respectively, and the third - to the eighth input of the number register and the second trigger input. The group of outputs and the fourth output of the pulse distributor are connected respectively to the second group of inputs of the selector unit and the input of the correction unit. The number register input group is a device input group.

The drawing shows a block diagram of the device.

The device includes a register / number containing three tetrads of triggers, a distributor of 2 pulses, a selection block 3, a block 4

correction, register 5 delay and trigger 6.

Register / is intended for receiving a convertible parallel binary-decimal code, storing intermediate conversion values 30, as well as for issuing the final result of the conversion in a binary parallel code.

Distributor 2 generates pulses necessary for synchronization of operation of all nodes of the device.

Block 3 serves to alternately pass the contents of the tetrads onto the common block and is made in the form of AND elements for the bits of each tetrad.

Block 4 is designed to analyze and correct the contents of the tetrads and represents a combinatorial scheme, the relationship between the input and output signals of which is such that the input code combination, containing the contents of 8, 9, 10, 11 and 12 binary units, is reduced by 3 in block 4.

Register 5 is intended to store four-bit corrected information until the end of the correction cycle of this tetrad.

The trigger 6 is intended for temporary storage of the current values of the fourth bit of information from the output of the register 5.

The device works as follows.

The binary-decimal code of the number to be converted into binary code is located in the / register in each case.

After that, the contents of all the tetrads alternately, starting with the first tetrad (TI-T elements, flow through block 3 to block 4, where tetrad codes are analyzed and corrected if necessary. From the output of block 4, the analyzed information of the tetrad goes to register 5.

The fourth bit of information of the first tetrad from register 5 enters trigger 6 for temporary storage, and the first, second and third bits enter elements of the first tetrad of register /, respectively. The information of the second tetrad, and then the third tetrad, from register 5 enters register 1 with a shift from the previous location one digit to the right. The contents of the trigger 6 enters the TI element of the third tetrad. Thereafter, in the / register, in a parallel code, bits of a binary number equivalent to the binary-decimal number being converted are arranged.

The states and output of trigger 6 correspond to the values of the binary sequential code.

Thus, the device can be used to convert a binary code to a parallel and serial binary code.

Using a number register to receive a convertible binary-decimal number, to store intermediate conversion values, and also to produce the final result of the conversion, allowed one correction unit to be used for all tetrads, thereby simplifying the device and increasing its reliability.

The economic effect of using the proposed device increases with an increase in the number of bits of the number to be converted.

Claims (2)

1M. M. Sukhomlinov and V. I. Vykhovanets “Number Code Converters, ed. “Technique, Kiev, 1965, p. 104, fig. 32. 2. USSR author's certificate No. 404077, M. Kl.2 G 06 F of 10/07/91 (prototype).