SU732852A1 - Position code to large base code converter - Google Patents

Description

The invention relates to automation and digital computer technology and can be used to construct positional code converters with one arbitrary base to codes with any other large base. ⁵

A known converter of binary code to code with any other base, containing pyramidal adders of the values of all bits of a number with a new base, while the number of bits of the first adder, on which the least significant bit of a number with a new base is allocated, is equal to the digit capacity of the converted binary number [1]. ₅

The disadvantage of this converter is the high hardware costs.

. The closest in technical essence and the schematic is the code converter to the code with a large _m based vaniem comprising a register, two-bit subtracter, a control unit, a multiplication by a constant, whose input is connected to the output of register K-th bit (where K is - the number of discharges code to be converted) and with the first input of a two-bit subtractor, the second input of which is connected to the output of the (K – 1) -th bit of the register, the outputs of the constant multiplication unit are connected to the third and fourth inputs of the two-bit subtract, respectively For, in addition, the converter contains a group of AND elements for shifting code in the register [2].

The disadvantage of the converter is a relatively low speed. In it, the conversion of a K-row number is carried out in 2 K (K — 2) + 1 clock cycles.

The purpose of the invention is to increase the conversion rate.

This is achieved by the fact that the converter contains the first, second, third and fourth elements And, the first and second. OR elements whose outputs are connected respectively to the inputs of the Kth and first bits of the register, the first 'inputs of OR elements are connected respectively to the outputs of the first and second elements

And, and the second inputs - with the outputs of the third and fourth elements And, respectively, the outputs of the senior and younger bits of a two-bit subtractor are connected respectively to the first inputs of the first and second elements And, the second inputs of which are connected to the first output of the control unit, the outputs of the Kth and (K -1) th bits of the register are connected respectively with the first inputs of the third and fourth elements And, the second inputs of which are connected to the second output of the control unit.

In FIG. 1 shows a block diagram of the proposed device; in Fig.2 - diagrams of control signals generated by the control unit of the device when converting four-digit codes.

The code converter contains a K-bit R-ary register 1, where X is the base of the number system into which the code is translated, a two-digit subtracter 2, a constant multiplication unit 3, four AND 4, 5, 6, 7 elements, and a control unit 8. The output of the senior (K-th) bit 9 of register 1 is connected to the inputs of the block 3 of constant multiplication and the least significant bit 10 of subtractor 2. The output of the (K-1) -th bit 11 of register 1 is connected to the second input 12 of the subtracter 2. The output of the senior bit 10 subtractor 2 through the first element AND 4 and the element OR 13 is connected to the input of the least significant bit of the register. The output of the low order bit 12 of the subtractor through the second AND element 5 and the OR element 14 is combined with the input of the first high order bit 9 of register 1. The output of the bit 9 through the third element And 6 is connected to the low order bit of the register. The output of discharge 11 is connected through the fourth element And 7 to the discharge 9 of register 1. The control unit 8 is connected via bus 15 with elements 6, 7, and via bus 16 with elements 5, 4.

The operation of the converter is considered on the example of the conversion of K - bit codes at K = 4.

All circuits that are part of the device are designed to work with number codes in the number system with the basis with which you need to get the result; K - the bit code of the integer that needs to be converted will be prevented from register 1. The code of the digit stored in bit 9 of register 1 is sent to block 3, where multiplication by a constant equal to the difference of the number systems is performed. On the subtractor 2, the number code from the outputs of block 3 is subtracted from the upper two bits of the number code entering register 1.

In the first three clock strokes from block 8, bus 16 is applied to the elements And 4, 5 to enable elements 4, 5, as a result of which the difference code from the output of the subtracter 2 is written into register 1 so that the contents of the upper digit 10 of the subtractor 2 are written to the least significant bit of register 1, and the contents of bit 12 of the subtracter 2 are recorded in the high bit of register 1.

In the fourth cycle, the And signals, from the control unit 8, are sent via bus 15 from the control unit 8, as a result of which the contents of register 1 are shifted by one bit to the left, while the code stored in the high order 9 of register 1 is rewritten to the low order, and the code stored in bit 11 is recorded in bit 9 of register 1.

At the fifth and sixth clock strokes, a control signal is sent to busbars 15 and 7 via elements 15, and at the seventh and eighth clocks a control signal is sent to busbars 16 and 5 via elements 16, 5.

On the (K-1) -th step in register 1, a number code is obtained with a new base of the number system.

The conversion algorithm is constructed in such a way that at every K steps (starting from the first), K-1, K-2, etc. are sequentially processed. digits of the converted number. Subsequent K- (K-1), K- (K-2), etc. bits of the intermediate result of the conversion remain unchanged.

At 6 * 3 = 18 measures. Translate <6012> _n 10-7 = 3 6612 “18 —Ϊ <x> 10 8124 record with a shift 8 * 3 = 2 4 8124 ~ 24 record with a shift 7245 7 * 3 = 21 7245 21 log in with a shift 1455 1455 0 shift 4551 , 4 * 3 = 12 4551 12 record with a shift

3513 3 * 3 = 9 __3513 record with a shift

6132

-6132

Osdvig

1326 _1326 About shift 10

3261

3 * 3 = 9_3261 record with shift

36 g15

On the timing diagram of the control signals (FIG. 2), which are generated by the control unit 8, it is shown that in the first four clock cycles (K = 4) the bit codes are sent to a two-bit subtractor 2 and a multiplication unit 3 (i.e., arithmetic operations on the bit codes) only on the first three clocks and four, the control signals from the control unit 8 on these clocks25 are fed to clock bus 16. At the next clock (fourth), the control signal is sent to bus 15, i.e. only the intermediate result of the translation is shifted without arithmetic processing of the digits. In the next four clock cycles (5-8), signals from the control unit to bus 15 are received twice already (in 7 and 8 clock cycles), i.e. Two shifts are carried out without arithmetic processing 35, etc. Therefore, the number of 'repeated' shifts is determined by the translation algorithm and is equal to 1 ’(where i is the number of the translation cycle).

The proposed converter has 40 higher speed compared to known devices. It translates a K-bit number in (K-1) ² cycles, while the known device translates a K-bit number in 2K (K-2) +1 clock cycles. For example, a 12-bit code prototype device translates in 241 clock cycles, and the proposed converter in 121 clock cycles.

Claims (3)

And, and the second inputs - with the outputs of the third and fourth elements And, respectively, the outputs of the high and low bits of the two-bit subtractor are connected respectively to the first inputs of the first and second elements And, the second inputs of which are connected to the first output of the control unit, the outputs K- The first and (Kl) -oro register bits are connected respectively to the first inputs of the third and fourth AND elements, the second inputs of which are connected to the second output of the control unit. FIG. 1 shows a block diagram of the device; in fig. 2 shows control signal diagrams produced by the device control unit when converting four-digit codes. The code converter contains a K-time regular R-ary register 1, where K is the base of the number system into which the code is transferred, a two-bit subtractor 2, a block 3 multiplying by a constant, four elements AND 4, 5, 6, 7, block 8 controls . The output of the higher (K-th) bit 9 of register 1 is connected to the inputs of the block 3 multiplying by a constant and the younger bit 10 of the subtractor 2. The output (K-l) -oro of the bit 11 of the register 1 is connected to the second input 12 of the subtractor 2. The output of the high-order bit 10 of the subtractor 2 is through the first element AND 4 and the element OR 13 is connected with the input of the lower-order bit of the register. The output of the low bit 12 of the subtractor is through the second element And 5 and the element OR 14 is combined with the input of the first high bit 9 of the register 1. The output of the bit 9 through the third element And 6 is connected to the low bit of the register. The output of bit 11 is connected through the fourth element And 7 with the bit 9 of register 1. The control block 8 is connected via bus 15 with elements 6, 7, and through bus 16 with elements 5, 4. The conversion is considered by the converter K - different codes at K4. All the schemes included in the device are designed to work with codes of numbers in the number system and with the basis with which the result should be obtained; K - the digit code of the integer number that needs to be converted is interfered with register 1. The digit code stored in bit 9 of register 1 enters block 3, where multiplication takes place by a constant equal to the difference of the bases of the number systems. On the subtractor 2 of the two high-order bits of the number code entering register 1, the code of the number coming from the block outputs is subtracted 3. In the first three clock cycles of block 8, the resolving potential is applied to the elements I 4, 5 through the bus, resulting in the difference code from the output of the subtractor 2 being written to register 1 so that the contents of the high bit 10 of the subtractor 2 are written to the youngest register bit 1, and the contents of bit 12 of subtractor 2 are recorded in the start bit of register 1. In the fourth clock cycle, the enable signal is sent to elements 6, 7 of control unit 8 via bus 15, resulting in a shift of register 1 by one bit d to the left, with the code stored Ice in the higher bit of 9 register 1 is rewritten to the lower bit, and the code stored in bit 11 is written to the bit 9 of register 1. At the fifth and sixth cycles from block 8, the control signal to the elements And 6, 7, and at the seventh and eighth cycles, the control signal on bus 16 goes to elements AND 4, 5. At (K-1) cycle in register 1, a number code is obtained with a new base of the number system. The transformation algorithm is constructed in such a way that K-1, K-2, etc. are sequentially processed at every K steps (starting from the first). bits of the number to be converted. Subsequent K- (K-1), K- (K-2), etc. the bits of the intermediate result of the transformation remain unchanged. Example. Move - 6612 record with shift record with shift 7245 7245 21 record with shift 1455 О. recording with cnBKTOt .. 3513 9 3513 O9 recording with offset 6132 .6132 О 1326 .1326 3261 9 09 recording with offset 2361 In the timing diagram of the control signals (FIG. 2), which are formed by control unit 8, it is shown that in the first four ticks () the bit codes are fed to the two-bit subtractor 2 and multiplier 3 (t, e, arithmetic operations over the years of bits are performed) only in the first three cycles and four, the control signals from the control unit 8 are received on these cycles on the clock bus 16. In the following clock cycle (quarter), the control signal arrives at bus 15, t, e, only the intermediate result of the translation is shifted without arithmetic processing of the bits. For the next four cycles (5-8) signals from the control unit to the bar 15 are already received twice (at 7 and 8 cycles), t, e, Two shifts without arithmetic processing are performed, and t, e. Consequently, the number of repeat shifts is determined by the translation algorithm and is i (where i is the number of the translation cycle). The proposed converter is faster than the known devices. It translates the K-bit number per (K-1) tactor, while the known device translates the K-bit number in 2K (K-2) +1 clock cycles. For example, the 12-bit code of the device-proto 7 type translates into 241 cycles, and the proposed converter into 121 cycles. Claims of the position code to a large base code containing a register, a two-bit subtractor, a control unit, a block multiplied by a constant, the input of which is connected to the output of the K-th register bit (where K is the number of bits of the code being converted) and the two-bit subtractor's input input, the second input of which is connected to the (Kl) -oro register bit output, the outputs of the multiplication unit by a constant are connected, respectively, to the third and fourth inputs of the two-bit subtractor, characterized in that At the conversion rate, it contains the first, second, third and fourth elements AND, the first and second elements OR, the outputs of which are connected respectively to the inputs of the Kth and first bits of the register, the first inputs of the elements OR are connected respectively to the outputs of the first and second elements And, and the second inputs - with the outputs of the third and fourth elements And, respectively, the outputs of the high and low bits of the two-bit subtractor are connected respectively with the first inputs of the first and second elements And | the second inputs of which are connected to the first input of the control unit, the outputs of the K-th and (K-l) -oro register bits are connected respectively to the first inputs of the third and fourth And elements, the second inputs of which are connected to the second output of the control unit. Sources of information taken into account in the examination 1, USSR Author's Certificate No. 315176, cl. G 06 F 5/02, 1970, 2, USSR Author's Certificate NO 485444, cl. G About F 5 / O2, 1974. Uj l and ± 1 {. Clock P p p p p p p p ri p itMne / fibCbl inn P P 1i 14 J i .g 15 i6 Fig 1 n A n FIG. 2