SU1292187A1 - Binary-coded decimal code-to-binary code converter - Google Patents

Abstract

The invention relates to computing and can be used to construct a conversion (/) C.

Description

binary numbers. The aim of the invention is to simplify the converter. The goal is achieved by the fact that a binary-decimal-to-binary code converter containing code converters 8, A, 2, 1 to code 4, 2, 2, 1 and rus, each of which implements a step of the Horner algorithm, is entered

The invention relates to computing and can be used to build converters of decimal numbers into binary ones.

The purpose of the invention is to simplify the converter.

The drawing shows a block diagram of the proposed converter for the case of converting a four-bit binary decimal code.

The converter contains adders registers 2, switches, converters of a one-bit binary-decimal code 8, 4, 2, 1 into code 4, 2, 2, 1, inputs of decimal digits of the converter, input 6 of the logical zero of the converter, outputs 7 of the highest converter bits, output 8 of the lower bit converter, input Record-transfer 9 converter.

The basis of the proposed device for converting a binary-binary code into a binary one is based on the following principle. Let the source operand be an integer binary-decimal number, where d is a k-decimal digit, represented by a binary code with weights of 8, 4, 2, 1 (1 k 6 4). Then the binary equivalent B of the initial decimal number D can be calculated by the following iterative formula:

B ((d4-1010 + d,) 1010 + d2) -1010 + d,

(-

S,

switch group 3.1-3.4, register group 2.1-2.4 and feedbacks from the transfer outputs of adders 1.1-1.3 through the corresponding switches to the inputs of the lower bits of the registers. This provides a series-parallel operation with the simultaneous formation of a group of binary bits. 1 ill., 1 tab.

The sum S ,, is a 7-bit binary number, the sum S is a 10-bit and the sum S is a 14-bit binary number. In the proposed device, the value of the sum S0 is formed at the outputs of the third adder L in three binary bits in one operation cycle of the device, and first the output of the sum Sg from the second to the fourth and then the next at the outputs of the adder P is the value of the bits of the sum S from the fifth to the seventh. Value first

the (youngest) bit of the sum S is equal to the value of the low bit bit of the digit dj and is not formed at the outputs of the summator Q. This value immediately goes to the corresponding input1,1 of the adder Ig s where

participates in the calculation of the value of Sj.

Similarly, in the device using the second adder, l is formed within three clock cycles -; the sum Sj, ac using the first adder 1, for five cycles of operation of the device, we obtain the value of the sum S (which is

binary equivalent B of the original decimal D.

In order to simplify the calculation of cyMMjSg-StB, the proposed device itself uses the digit d of the source operand D in code 8, 4, 2, I, and all its other digits in code 4, 2, 2, 1.

The Converter operates as follows.

In the first cycle of work on the signal at its control input 9,

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is receiving a decimal operand from inputs 5 (-54 to registers 2, with only the highest digit of the decimal operand being written into registers without change in code 8, 4, 2, 1, all the other digits are pre-converted with help from converters 4 , -4h from code 8, 4, 2, 1 to code 4, 2, 2, 1, and only then written to registers in this code. At output 8, the value of the least significant binary digit of the result is formed. inlet 9, a control potential is established, which provides for the duration of the entire process. ca .preobrazovani receiving information registers with the second input switch 3, -34 (the second inputs of the fourth switch 34 from the input 6 receives a logic zero signals). In the second cycle operation at the outputs of the first adder 1 is formed zna

Note. The rectangles contain the values of bits, which are written into the corresponding bits of registers 2, -2, as well as the values of bits S, which are given on a coherent basis at outputs 7 and 8 (only significant figures are given).

In the first cycle of operation, the most significant bit of register 2 in the code is set at control input 9, 8, 4, 2, 1 (all other digits of the high potential generator and 50 times are converted by converters are received by decimal, operand from the inputs to the registers through the first (right) inputs of the switches (the registers are recorded at the first sync pulse of the result. At the end of the cycle). The highest digit of the tenth one clock cycle at the control input 9

 from code 8, 4, 2, 1 to code 4, 2, - 2, 1 and only then they are written to registers). At output 8, the value of the youngest binary-sided is formed (in the numerical example under consideration, it is equal to 9) is written to register 2 and the fourth (the most

the converter is set low potential for the rest of the operand conversion time.

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The second to fourth bits of the result, which arrive at the outputs 7. Next, four more clocks are performed, during which ten higher bits of the result are received at the outputs 7. Thus, a 14-bit binary equivalent of a 4-bit number is generated in the proposed device in six clocks, one of which clocks is used to load the original operand into registers 2, -24 of the converter.

The table shows a numerical example of converting a decimal number 9124 into a binary number 1000 1110 100100, with the contents of the first, second, third and fourth times being displayed in columns 1-6; Rows (right to left) of registers 2 after the end of each of the six cycles of operation of the device.

most significant) of register 2 in code 8, 4, 2, 1 (all other digits are first converted by the converters of the go result. At the end of the first clock cycle at the control input 9

 from code 8, 4, 2, 1 to code 4, 2, - 2, 1 and only then they are written to registers). At output 8, the value of the lowest-order binary converter is set to a low potential for the remainder of the operand conversion time.

five

- During the second clock cycle, the second, third, and fourth bit Sg values are calculated, the first two of which are involved in the calculation on adder 1. The second and third bit values generated in the second cycle are involved in the same clock cycle. S (whose values of the three bits (S, S and S) are removed from output 7, after the second one is completed, the registers are entered into, S, S, where, 3.4 respectively, and the values of output transfers from adders 1 - C to calculate on them in the third cycle the values of the three following p sp rows Sn, Sg, Pj, where., 2.3. The input register 2 to 6 za- pisyvaats zero information,

In the third cycle on the accumulators 1, the values of Sg, Sj, S are calculated from output 7, and the values of sj, S, Sj are removed. At the end of the third clock cycle, registers 2, and 2 are written to the values of bits S and 8.3. In register 2 3, the zeros from the output of register 2 are written, and in register 2, the zero information from input 6 is again recorded. In subsequent cycles, the converter operates in the same way. In the sixth clock cycle at output 7, the most significant bits of the binary number appear.

In a similar way, a device can be developed that forms in a single gakt g binary.

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m (-g, where m is the total number of binary digits of the result, xj is the nearest integer greater than or equal to x), with the duration of a clock being determined by the time information is written to the register and the information delay on a single switch and g single-digit binary adders .

Formula of invention

The converter of a binary-decimal code into a binary one containing (n-1) adders and () converters of a one-bit binary-decimal code 8, 4, 2, 1 to the code 4, 2, 2, 1 (where n is the number of decimal bits) and the inputs of the i-ro (i l -: - n--1) converter single bit binary-decimal code 8, 4, 2.1, code 4, 2.2, 1 are connected respectively to the inputs of the i-ro binary de.

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the main bit of the converter, the output of the lower bit of the first converter of the one-bit binary-decimal code 8, 4, 2, 1 to the code of 4, 2, 2, 1 and the outputs of the first adder are connected respectively to the outputs of the converter, the outputs of the two lower bits The j-ro of the adder () is connected respectively to the first inputs of the two old Esch bits (jl) -ro of the adder, characterized in that, in order to simplify the converter, it contains n registers and n switches, the control inputs of which are connected to the Record input the transfer of the converter, the inputs of three the most significant bits of the nth decimal bit of which are connected respectively to the first group of inputs of the nth switch, the second group of inputs of which is connected to the input, the logic zero of the converter, the output of the high bit of the i-ro register is connected to the first input of the lower level and the second input of the senior bit of the 1st adder, the transfer input and the second group of inputs of the two lower bits of which are connected respectively to the outputs of the three lower bits of the i-ro register, whose inputs are connected respectively to the outputs of the i-ro switch, ne Va group of inputs of three lower-order bits of which is connected respectively to the outputs of the three higher-order bits of the i-ro converter of the 1-bit binary-decimal code 8, 4, 2, 1 to code 4, 2, 2, 1, the first input of the high-order bit i The -ro switch is connected to the low-order output of the (i + +1) th converter of a 1-bit binary-decimal code 8, 4, 2 1 to 4, 2, 2, 1 code, the second low-input input of the i-ro switch is connected with the transfer output of the i-ro adder, the bit outputs of which are connected respectively to the second group of inputs of the three most significant bits (il) -ro com {utatora, the second group of inputs of the three most significant bits of the (n-1) -th switch is connected respectively to the outputs of the n-th register; the outputs of the two lower-order bits of which are connected respectively with the first group of inputs of the two most significant bits of the (n-1) th adder, the first input of the highest bit of the n-th switch is connected to the input of the lower one. About 712921878

The auxiliary bit of the nth decimal spread is connected to a number of converters, the inputs of the nth switch of the nth switch, respectively.

Claims (1)

Claim A binary-decimal to binary converter containing (n-1) adders and (n + 1) converters of a single-digit binary decimal code 8, 4, 2, 1 to 4, 2, 2, 1 (where n is the number of decimal places ) _? and the inputs of i-ro (ί = 1τη— 1) of the converter of a single-bit binary decimal code 8, 4, 2,1 to code 4, 2,2, 1 are connected respectively to the inputs of i-ro binary-dec. c. of the decimal place of the converter, the low-order output of the first converter of the single-bit binary decimal code 8, 4, 2, 1 to 5, the code 4, 2, 2, 1 and the outputs of the first adder are connected respectively to the outputs of the converter, the outputs of the two least significant bits j-ro adder (j = 2in ^_ l) connection! respectively, with the first inputs of the two aging bits (jl) -ro of the adder, characterized in that, in order to simplify the converter, it contains η registers and η 15 switches, the control inputs of which are connected to the Record-transfer input of the converter, the inputs of the three high-order bits ~ decimal place of which is connected, respectively, to the first group of inputs of the ηth switch, the second group of inputs of which is connected to the input. logic zero of the converter, the output of the highest bit of the i-ro register 25 pa is connected to the first input of the least significant bit and the second input of the highest bit of the ι-th adder, the transfer input and the second group of inputs of the two least significant bits of which are connected 30 respectively with the outputs of the three least significant bits of the i-ro register , the inputs of which are connected respectively to the outputs of the i-ro switch, the first group of inputs of the three least significant bits 35 of which are connected respectively to the outputs of the three most significant bits of the i-ro converter, single-bit decimal to yes 8, 4, 2, 1 to code 4, 2, 2, 1, the first input older than the 40th bit of the i-ro switch is connected to the low-level output of the (i + +1) th converter of a single-bit binary decimal code 8, 4, 2 , 1 to code 4, 2, 2, 1, second input 45 low-order bits of the i-ro switch is connected to the transfer output of the i-ro adder, the bit outputs of which are connected respectively to the second group of inputs of the three high-order rows (il) -ro of the switch, the second group of inputs of the three high-order bits (nl) -ro of the switch are connected respectively with the outputs of the ηth register, the outputs of the two least significant bits of which are connected respectively to the first group of inputs of the two highest bits of the (nl) -ro adder, the first input of the highest bit of the ηth switch is connected to the input of the least significant 1292187 8 digits of the ηth decimal resolution are connected respectively to a number of converters, the inputs of the ηth are the outputs of the ηth decimal switch.