SU720424A1 - Binary-decimal to sequential binary code converter - Google Patents

Description

The invention relates to digital computing, can be used in computers and specialized automatic devices. A binary-to-binary code converter is known which contains the input code register, the equivalent driver, the pulse distributor, the summing tetrad and the output (Ij. A disadvantage of the known device is the inability to convert negative numbers, a relatively large amount of hardware and a slow response resulting from sequential analysis. all binary bits for each decimal bit. The closest to the proposed converter is binary-decimal code to binary, containing the input code register, pulse distributor, adder, adder register and shaper equivalent equivalents / the first group of inputs is connected to the outputs of the input code register, the second group of inputs with the output of the pulse distributor, and the outputs of the imager are connected to the first group of inputs of the adder, the outputs of which are connected to the inputs of the adder register 2 /. A disadvantage of this device is the impossibility of converting negative numbers and the relatively large amount of equipment associated with zovaniem polnorazr sum Matora-stand. The purpose of the invention is to simplify the device and allow the conversion of negative numbers. The goal is achieved by adding an additional register to the device, the inputs of which are connected to the first group of outputs of the register of the adder, and the outputs - to the second group of inputs of the adder, a character trigger, two AND elements and an output OR, the inputs of which are connected to the outputs of the AND elements, the first the inputs of which are connected to the outputs of the sign trigger, the second inputs of the elements I are connected to the output 5 and MPa. the first and second bits of the register of the adder, respectively, the transfer input of the adder is connected to the unit output of the sign trigger. Time shaper: A number of equivalents contains a group of elements I,

a group of OR elements and an adder of the number of units whose inputs are connected to the outputs of the OR elements. input elements OR are connected from the output of elements I.

Fig. 1 shows a structural electrical converter circuit.

The transducer contains cyMwiatop 1, shaper of poreal equivalents 2, register-entry code 3, pulse distributor 4, register of adder 5, elements 6, 7, output element 8, sign trigger 9, register 10, selection block; the leading edge of the pulse 11, the block selection of the back of the pulse 1

Fig. 2 shows a structural electrical circuit diagram of a unit of equivalent equivalents for a four-bit binary-decimal number.

Table 1 shows the binary equivalents of binary numbers (but decimal numbers.

Table 2 illustrates the process of converting a number to ± 6975, respectively, direct and optional, binary code.

The appendix contains the algorithm for converting binary-decimal numbers to binary code.

The converter of the constructions is as follows: the inputs of the K-raer of the adder 1 (term A) soybean, zinen, s with the driver's outputs, equivalent to 2, The number of the generator's outputs, and hence the width of the curtain depends only on the width of the forward binary - tenth code. The inputs of the 14-WATER 2 are connected on one side to the outputs of the register of the input code 3 and on the side shea - from the output of the pulse distributor 4, the number of outputs of which is equal to the number of bits of the converted binary code. The output of each bit of the adder, taking into account the transfer, is connected to the input of the corresponding bit of the register of the adder 5. The outputs of the low-order bit of register 5 are connected by elements 6, 7 to the output element 8. The second inputs of the elements Comm. Inna to the outputs of the sign trigger of the transformed Numbers 9 "The unit output of the character trigger is connected to the sc 5 input transfer port of the first bit C5 Mmator. The remaining bits of the register of the adder are connected to the inputs 10, intended for the crank of the second term (), the outputs of the register 10 are connected to the inputs of the adder ,.

The proposed device works as follows. On the command Start of conversion, a single pulse sets the distributor I1. Pulses 4 and registers 5, 10 to Zero. The distributor starts to pass to its input a continuous sequence of pulses allocated on the trailing edge of the input frequency pulses using block 11.

In the first column of the table. 1 shows the weights of each bit of a binary single code. The first line contains the numbers of bits of the binary code, in the second - their weights. On the field table. 1 - the weight of each binary-decimal place, as well as the weight of the character located in the last line, are represented in binary code.

To convert a binary-decimal code to a serial binary code, it suffices to add in the binary system the values of the bits of the binary-decimal code in each vertical column, starting with the second, taking into account the amount in the previous column, shifting it by one bit to the right.

The first pulse fg ,, after the arrival of the command Start of the conversion, at the output of the 1C of the pulse distributor, a signal is generated, with the help of which the discharge state of the .10 ° binary-decimal code and the value of the sign trigger o are polled

 If the number to be converted is negative, the sign trigger value is one.

A binary K-bit code (term A) is formed at the output of the splitter equal to the value of the bit.

2 ° -lO. At this time, the binary inputs pGniCTpa 10, equal to zero (term B), arrive at the second inputs of the adder. After adding the two terms (Au B), taking into account the sign at the output of the adder, we get a code equal to the value of the discharge –10 ° or aj 2 ° -10 + -1.0 ° with the negative conversion number. This code is recorded by the second pulse, allocated on the leading edge from the input frequency by block 12, S register 5, the low-order values of which are accessed, respectively, at the inputs of the And b and 7 elements, controlled by the sign trigger 9. The second to impulses fd, Register 5 is rewritten to register 10 without a least significant bit.

2C

On signal

the pulse distributor begins the formation of binary bits, for which it is polled according to the table. 1 value of bits in 2lO, aj -2 10 and sign trigger value. If the values of bits are one, the binary k - bit code of the term A is two. The term B in this case depends on the sign of the number to be converted and can take the values

silt

. The third impulse fII, the sum

The spares of A and B, taking into account the sign, are recorded in register 5. Further operation of the converter is similar to that described. The converter polls the bits of the binary-decimal code according to the signals of the pulse distributor in accordance with the table. 1, adds and gives out: values of bits. Suppose you need to convert a positive binary number to

 djC3b.jaj

diCtb, at N About IT 1001 O 111 0101

 69752 i о

 ten . 10 10 10 When a maximum four-digit binary-decimal number is converted, a 14-bit binary code is obtained, therefore, the time distributor must produce fourteen cycles.

The maximum number at the output of the former is six, which is determined by the seventh and ninth columns of the table. 1, in which, with a certain binary-decimal code, there will be six one-weight units. Therefore, the A condition will be represented. in the form of a three-bit binary code.

The unit of equivalent equivalents (Fig. 2) contains a group of 13 elements AND, the inputs of which are connected to the outputs of the register of the input code and certain outputs of the pulse distributor, a group of 14 elements OR, whose inputs are connected to the outputs of the elements AND, and the adder of the number of units 15 .. . 5 In table. 2 displayed in detail

the process of converting positive and negative numbers.

The additional code of the p-bit binary number is equal to the direct code

The Q of this number is plus a p-binary binary with units in all bits followed by inversion.

In this connection, the trigger value is constantly applied to the transfer input (P) of the low bit of the adder.

 sign, column 36 of table 2 contains the additional binary code of the negative convertible number

Np 10 010 Oil 000001 Oper, target: L00000000000000,

00110110011111.

10010011000001

The device can convert both positive and

5 negative numbers. The amount of equipment in it is reduced several times by replacing the full-digit adder with an adder with a small size, while maintaining the current

By the same speed. Transformation

combined with the output of the result bits.

Jad / iuu, a /

"M

at

Claims (2)

ir Claim 1. Inventory binary-decimal}; code into serial binary, containing the input code register pulse distributor, adder, adder register and bit equivalent generator, the first group of inputs of which is connected to the outputs of the input code register, the second group of inputs - with the outputs, the pulse bodies are distributed, and the outputs of the former are connected to the first group of inputs of the adder, the outputs of which are connected to the inputs of the register of the adder, which in order to simplify the circuit and in the liver, the possibility of converting negative numbers, an additional register is entered in it, the inputs of which are connected to the first group of outputs of the register of the adder, and the outputs from the second group of inputs of the adder, the trigger of the sign, two AND elements and the output element Aa-2 ar l, -2 cTlZ a -23 ar-2 ° Bg-s Yyyy cfn- ci .f (0iHj . - (2iu) four. J. w OR, the inputs of which are connected to the outputs of the AND elements, the first inputs of which are connected to the outputs of the sign trigger, the second inputs of the elements AND are connected to the outputs of the lower first and second digits of the sum register, respectively, the transfer input of the adder is connected to the single output of the sign trigger. 2, the converter according to claim 1, which is characterized by the fact that in it the shaper of equivalent equivalents contains a group of elements AND, a group of elements OR and an adder of the number of units, whose inputs are connected to the outputs of the elements OR, the inputs of the elements OR are connected to the outputs elements I. Sources of information taken into account in the examination 1. Author's certificate of the USSR No. 393739, cl. -C 06 F 5/02, 1971. 2. Authors certificate of the USSR, 470803, cl. G 06 F 5/02, 1973. K-.g Tl -I g.f4.r. “- W .2СзЧ- -11 g..f2 ft4-r; j 5 / -f f tfi4- " Nachprepreo5r. - i- l nr5l Ш1 7.3M ll2J3i4 i {-j