SU746505A2 - Device for raising binary numbers to the third power - Google Patents

Description

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The invention relates to computing, can be used in various digital functional converters.

According to the main law auth. Thereafter, No. 49И29 a device for raising binary numbers to the third power is known, which contains a binary counter, delay elements Q, two adders, groups of elements I, the input bus of the device connected through two elements of delay to one of the inputs of the first group of elements And, the other inputs of which connected to the output1M of the first adder, and the outputs - to one of the inputs of the second adder, the output of the second delay element is connected to one of the inputs of the second group of elements And, others20

the inputs of which are connected to the outputs of the binary counter, and the outputs are connected to one of the inputs of the first sump, the input bus is connected to the input of the second adder and to one input 25 of the third group of I elements, the other inputs are connected to the outputs of the binary counter, and the outputs to others the inputs of the first adder, the output of the first delay element pod-, JQ

the keys also to the input of binary counter 1,

However, the known device has limited functionality, since it cannot be calculated, the function

The aim of the invention is to extend the functionality due to the possibility of extracting a third degree root from a parallel binary code.

The goal is achieved by introducing a pulse generator, an I element, a comparison circuit in the device for raising binary numbers to the third power, the first group of inputs of which is connected to the information input of the device, the second group of inputs is connected to the outputs of the second adder, and the output is connected to the first input element And, the second input of which is connected to the output of the pulse generator, and the output with the corresponding inputs of the second adder, the second delay element and one of the inputs of the elements And the third group.

FIG. 1 uses the principle of mutually reversible functions Y X rf Y Vx (Fig. 1), i.e., symmetry

these functions are relative to the bisector of the first and third coordinate angles. From these graphs it can be seen that in order to find the root of the third degree for this argument OX, i.e. HdU, it is necessary to find such an argument OX / i (OX,), the third power of which X, Y5 would be equal to the initial argument,. those. HD OX, while HgUg Yy Thus OX L / X, In Fig.2blok diagram of the proposed device.

The device contains information input If comparison circuit 2, element 3, pulse generator 4, binary counter 5, adders 6-7, groups of elements 8-10, delay elements 11-12.

The device works as follows

In the initial state, binary counter 5, adders are set to O. At input 1, a zero code is applied, comparison circuit 2 fixes the equality of compared codes (input and code from adder 7) and outputs a signal that closes the element and 3 at the first input. As soon as input 1 receives a parallel code 1 from which a third degree root is to be extracted, the comparison circuit will fix the inequality of the M codes and the zero code recorded in the adder 7, and issue a signal to the eu-output. This signal is sent from the cell IZ, pulses from the pulse generator 4 will begin to pass. By the arrival of the first pulse from the pulse generator, 1 is added to the contents of the adder 7, and the contents of binary counter 5 are transmitted through the group of elements I-10 (third group) and added to the contents adder 6. An input pulse passes through delay element 12 and opens a group of elements AND 9, (the second group) through which the contents of binary counter 5 is transmitted to the input of adder b shifted one digit to the left.

Thus, the threefold contents of binary counter 5 are added to the previous value in the adder B, then the input pulse passes through the delay element adds the low-order H to the content of the binary counter and opens a group of elements AND 8 (the first group) to allow the transfer of the code output / adder 6 to the input of adder 7 with a shift to one bit to the left. After the arrival of N pulses in binary counter 5 and in adder 7, they are throbbed. the values of H-, and H, respectively.

Code number Nj | compared with source code N by comparison circuit. At some specific value of Nj

Q (Nj N) of the sequential code NV will turn out to be the same as the power of this number. S N, is equal to the original parallel code NI, i.e. N N 3N. In this case, the comparison circuit will fix the equality of the code in the adder

5 7 and the N code from the single inputs and will output on its output the signal O, SigO

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from the comparison output

closes the element And 3 and thereby stops the passage of pulses. Nj code

0, fixed in binary counter 5, will be a third-degree root from the input parallel (binary binary code N ,,, T.e.N I / N,

Thus, the proposed device allowed us to expand the functionality of the capabilities of the known device without significant hardware costs.

Claims (1)

Invention Formula Device for raising binary numbers to the third degree according to aut. swith No. 491129, characterized in that, in order to extend the functionality due to the possibility of extracting a third-degree root from a parallel binary code, a pulse generator, an AND element, a comparison circuit, the first input group of which is connected to the information input of the device, the second group are entered into the device inputs - with the outputs of the second adder, and the output is connected to the first input element And, the second input of which is connected to the output of the pulse generator, and the output with the corresponding inputs of the second adder, the second delay element and with one of the inputs of the element And the third group,  Sources of information taken into account in the examination 1, USSR author's certificate  491129, class G 06 F 7/38, 1974,