SU1076912A1 - Device for calculating values of function (x-y)y - Google Patents

Abstract

A device for calculating the function (xy) / y, containing two registers, two totalizers-subtractors, a block of analysis of the sign of the difference and a control unit containing a pulse generator, element AND, element OR, subtractive counter, decoder zero, trigger, element NOT and a delay element, the output of the pulse generator is connected to the first input of the element I, the second input and the output of which are connected respectively to the trigger output and the input of the delay element whose output is connected to the input of the subtracting counter, the output of which is through the zero decoder connected to the first input of the OR element, the second input and output of which are connected respectively to the output of the element and the input to set the trigger to zero. the installation input into the unit of which is connected to the input of the NOT element and the output of equality of the values of the difference sign analysis block, the output of the control element AND of the control block is connected to the clock inputs of the first and second registers, the output of the delay element is connected to the clock inputs of the first and second adders, subtractors the inputs of which are connected to the output of the sign of the difference of the block of the analysis of the sign of the difference, the first and second inputs of which are connected respectively to the outputs of the first and second adders-subtractors, the inputs of the initial set Oki which are connected respectively to the inputs of the first and second arguments of the device, the output of the second register is connected to the input of the first totalizer, the input of the initial installation of the second register is connected to the input of the second argument of the device, characterized in that, in order to expand the scope due to the possibility of calculating the relative error ( -y) / ij, the output of the sign of the difference of the block of the analysis of the sign of the difference is connected to the information input of the first register, the output of which is connected to the output of the device, the output of the second th register coupled to the data input of the second adder-subtracter.

Description

The invention relates to digital computing and can be used in digital measuring devices and information processing systems.

A digital function converter is known, comprising adders, subtractors, registers, a unit for storing constants, an analysis unit, and a control unit l.

The disadvantage of this device is the impossibility of calculating the value of the relative error.

The closest to the present invention is a digital functional converter containing an analyzing unit, two totalizers-subtractors and a shift register, a control unit, the first and second outputs of the control unit being connected to the control inputs of each of the shift registers and clock inputs of each of the adders - the subtractors, respectively, whose outputs are fed to the inputs of the analysis unit, and its two outputs are connected to the subtractors and the control unit. Each of the two inputs (variables x and y) is associated with inputs of the recording of adders and shift registers. This converter allows you to find the quotient from dividing the sum of squares of input variables by their sum

) /lx.H).

A disadvantage of the known devices is the limited scope due to the impossibility of calculating the quotient of dividing the difference of two numbers into one of them (relative error).

The purpose of the invention is to expand the field of application of the device due to the possibility of calculating the relative error {K-H 5/4

 The goal is achieved by the fact that in the device for calculating the function (xy) / y containing two registers, two adders, a subtractor, a difference sign analysis unit and a control unit containing a pulse generator, an AND element, an OR element, a subtracting counter, a decoder zero , a trigger, an NOT element and a delay element, the pulse generator output being connected to the first input of an And element, the second input and output of which are connected respectively to the trigger input and the input of the delay element whose output is connected to the input of the detracting counter, out one of which is connected to the first input of the OR element via the zero decoder, the second input and output of which are connected respectively to the output of the element NOT and the input of the setting to the zero of the trigger, the installation input to the unit

which is connected to the input of the element NOT and the output of equality of the values of the difference sign analysis block, the output of the element AND of the control block is connected to the clock inputs of the first and second registers, the output of the delay element is connected to the clock inputs of the first and second adders-subtractors whose control inputs are connected to the output the sign of the difference block analysis of the sign of the difference, the first and second inputs of which are connected to the outputs of the first and second adders-subtractors, the inputs of the initial installation of which are connected to the inputs, respectively The first and second arguments of the device, the output of the second register are connected to the information input of the first adder-subtractor, the initial setup of the second register is connected to the second input of the device argument, the output of the difference sign of the difference sign analysis block is connected to the information input of the first register, the output of which is connected to the output of the device, the output of the second register is connected to the information input of the second adder-subtractor.

Fig. 1 is a block diagram of the device according to the invention; Fig. 2 is a block diagram of a control unit.

The device contains summators 1 and 2, registers 3 and 4, a block of 5 analysis of the sign of the difference and control block 6, which includes a pulse generator 7, an AND 8 element, an OR 9 element, a delay element 10, a subtracting counter 11, a decoder 12 zero, a trigger 13 and the item is NOT 14.

The following iterative formulas are related to the operation of the device

).

L-, with Xj-tjj with O ;,

.S-9i-y- i} + Г-У, Ч, -Ч2 5

where 3 1,2 ,. .., (n-1) is the iteration number, and is the number of bits of the values X and 1 |.

The proposed device works as follows.

Before starting work in the second register 4 and in the second adder-subtractor 2, the operand is entered in the first adder 1 - X. The clock generator in the control block b is turned on. From the output of the element 8 of block 6, the clock pulse goes to the clock inputs of registers 3 and 4 and shifts their contents one bit to the right (register 4) and to the left (register 3). Then, from the output of the delay element 10 of block 6, the same clock pulse delayed in time arrives, which supplies the contents of register 4 to the input of adders 1 and 2, where it is subtracted or added to the previous values of adders. Moreover, the choice of addition or subtraction for a specific adder is performed by block 5 for analyzing the sign of the difference by difference 5 j - yj - In case it is less than zero, adder 1 works in addition mode, and adder 2 subtracts. Otherwise, their modes mutually change. Mode

determined at each clock. After running (tl-1) iterations in the first shift register, the relative error 2 is contained (the Z being represented in (n-15 least significant bits of the first register. Range of change 2 from 2 to minus 1. x 4 and |, resulting in a value outside this range, you must enter a scaling y. The absolute error of the calculation will be equal to

1

Claims (1)

DEVICE FOR CALCULATING THE FUNCTION (xy) / y, containing two registers, two adders, a subtractor, a difference sign analysis unit and a control unit containing a pulse generator, AND element, OR element, subtracting counter, zero decoder, trigger, element NOT. and a delay element, wherein the output of the pulse generator is connected to the first input of the And element, the second input and output of which are connected respectively to the output of the trigger and the input of the delay element, the output of which is connected to the input of the subtracting counter, the output of which is connected through the zero decoder to the first input of the OR element, the second input and output of which are connected respectively to the output of the element NOT and the input of the zero setting of the trigger, the input of the unit to which is connected to the input of the element NOT and the output of the equality of values of the analysis unit On the other hand, the output of the AND element of the control unit is connected to the clock inputs of the first and second registers, the output of the delay element is connected to the clock inputs of the first and second adders-subtracters, the control inputs of which are connected to the output of the difference sign of the difference sign analysis unit, the first and second inputs of which are connected respectively, with the outputs of the first and second adders-subtracters, the inputs of the initial installation of which are connected respectively with the inputs of the first and second arguments of the device, the output of the second register with is single with the input of the first adder, the input of the initial setup of the second register is connected to the input of the second argument of the device, characterized in that, in order to expand the scope due to the possibility of calculating the relative error c, the output of the difference sign of the difference sign analysis unit is connected to the information input of the first register the output of which is connected to the output of the device, the output of the second register is connected to the information input of the second adder-subtractor.